Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

SYSTEM PERFORMANCE
48-bit result. For example, a “36’b 0101
1111 1111 10101 1101 1110 1111 1000
1110” result would become “48’b 0000
0000 0000 0101 1111 1111 10101 1101
1110 1111 1000 1110”.
Precision Synthesis supports this automatic
sign extension when any of the
DSP48 operators are inferred. This is a
simple concept, but very powerful, because
it allows you to perform wider arithmetic
operations without having to manually set
the correct bus width for the output result.
Accumulator (Adder/Subtractor)
The adder/subtractor stages are functions
of the inputs, which are driven by the
upstream multiplexers, carry-select logic,
and multiplier arrays. The CIN, X multiplexer
output, and Y multiplexer output
are always added together. You can control
this combined result to be selectively added
to or subtracted from the Z multiplexer
output: Adder Out = (Z ± (X + Y + CIN).
Pipeline Registers
This is a unique advantage of the DSP48
block compared to other DSP FPGA architectures.
Each DSP48 slice contains the
following pipeline registers at each stage:
• One or two pipeline registers for A and
B inputs (AREG and BREG)
• One pipeline register at the output
multiplier stage (MREG)
• One pipeline register at the output
stage (PREG)
• One pipeline register at the C input
• One pipeline register for opmode and
other control signals
DSP48 Ports
The DSP48 slice input and output ports
support many common DSP and math
algorithms. Two direct 18-bit input data
ports are labeled A and B. As shown in
Figure 1, two DSP48 slices within a
DSP48 tile share a 48-bit input data port
labeled C. Each of them has one direct 48bit
output port labeled P, a cascaded input
datapath (B cascade), and a cascaded output
datapath (P cascade), providing a cas-
h0
18
18
0
B
X
+
caded input and output stream between
adjacent DSP48 slices.
Operating Mode
The 7-bit operating mode (opmode) inputs
provide a way for the design to change its
functionality from clock cycle to clock cycle
if desired. There are more than 40 dynamically
controlled opmodes, although you cannot
set all possible combinations (as
described in the Virtex-4 datasheet, www.
xilinx.com/bvdocs/userguides/ug073.pdf ). The
opmode bits can be optionally registered
under the control of the configuration
module top (h, B, P, clk);
parameter tap = 4;
parameter sub_in_width = 18;
parameter sub_out_width = 48;
`define sub_out_width 48
h1
input clk;
input signed[sub_in_width-1:0] B;
input signed[sub_in_width*tap-1:0] h;
output signed[sub_out_width-1:0] P;
// Wiring array declarations being used for internal signals
wire signed[sub_out_width-1:0] PCOUT_INT [0: tap-1];
wire signed[sub_out_width-1:0] PCIN_INT [0: tap-1];
mult_add U0 (.A(h[sub_in_width-1:0]),
.B(B), .clk(clk),
.PCIN(`sub_out_width'b0),
.PCOUT(PCOUT_INT[0]) );
generate
genvar i;
for (i=1; i < tap; i=i+1) begin : dsp48
mult_add UI (.A(h[i*sub_in_width+(sub_in_width-1) : i*sub_in_width]),
.B(B),
.clk(clk),
.PCIN(PCOUT_INT[i-1]),
.PCOUT(PCOUT_INT[i]) );
end
endgenerate
assign P = PCOUT_INT[tap-1];
endmodule
//========================================
module mult_add(B, A, PCOUT, PCIN, clk);
parameter sub_in_width = 18;
parameter sub_out_width = 48;
input clk;
input signed[sub_in_width-1:0] A,B;
input signed[sub_out_width-1:0] PCIN;
output reg signed[sub_out_width-1:0] PCOUT;
//a,b,m,and p pipelined registers
reg signed[sub_in_width-1:0] breg;
reg signed[sub_in_width-1:0] areg;
reg signed[sub_out_width-1:0] mreg;
always @ (posedge clk)
begin
areg