Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

Design Example: 1.5 volt LVCMOS 4mA, I/O, 100 aggressors shown.
Dr. Howard Johnson, author of High-Speed Digital Design,
frequently conducts technical workshops for digital engineers
at Oxford University and other sites worldwide.
Visit www.sigcon.com to register.
Best Signal Integrity:
7x Less SSO Noise
Virtex-4 FPGAs deliver the industry’s best signal integrity, allowing you to
pre-empt board issues at the chip level, for high-speed designs such as memory
interfaces. Featuring a unique SparseChevron pin out pattern, the Virtex-4 family
provides the highest ratio of VCCO/GND pin pairs to user I/O pins available in any
FPGA. By strategically positioning one hard power pin and one hard ground pin
adjacent to every user I/O on the device, we’ve reduced signal path inductance
and SSO noise to levels far below what you can attain with a virtual ground or
soft ground architecture.
The Industry’s Highest Signal Integrity,
Proven By Industry Experts
Incorporating continuous power and ground planes, plus integrated bypass
capacitors, we’re eliminating power-supply noise at its source. In addition, we
provide on-chip termination resistors to control signal ringing. The lab tests
speak for themselves. As measured by signal integrity expert Dr. Howard Johnson,
no competing FPGA comes close to achieving the low-noise benchmarks of
Virtex-4 devices.
Visit www.xilinx.com/virtex4/sipi today, and choose the right high-performance
FPGA before things get noisy.
The Programmable Logic Company SM
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