Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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Power Estimation Tools Xilinx provides power estimation tools in two forms: a pre-implementation tool called Web Power Tools and a post-implementation tool called XPower. The Web Power Tools at www.xilinx.com/power provide power estimation based on ballpark estimates of logic usage. With this, you can get a power assessment with only a design utilization estimate – no actual design files. XPower is a post-implementation tool that analyzes the actual device usage and, in conjunction with actual post-fit simulation data (in the form of a VCD file), delivers Figure 2 – XPower accurate power data. With XPower, you can analyze design changes for impact on overall power without touching a piece of silicon. Web-Based Power Tools Web-based power estimation is the quickest and easiest way to get an idea of device power consumption early in the design flow. A new version of these tools is released every quarter, so information is current, and no installation or downloading is required – just an Internet connection and a web browser. You can specify design parameters and save and load design settings, eliminating the need to re-enter design parameters with iterative use. Just an estimate of design behavior and a target device will get you started. XPower – Integrated, Design-Specific Power Analysis XPower, a free part of all Xilinx ISE design tool configurations, allows you to get a much more detailed estimate of your design-based power requirements. XPower estimates device power based on a mapped or placed and routed design. XPower calculates an estimate of power with an average design suite error of less than 10% for mature in-production FPGA and CPLDs. It considers device data along with your design files and reports estimated device power consumption at a high level of accuracy, customized to your specific design information. XPower is integrated directly into ISE software and gives hierarchical and detailed net power displays, detailed summary reports, and a power wizard that makes it easy to run for new users. XPower can accept simulated design activity data and runs in both GUI and batch mode (Figure 2). XPower considers each net and logic element in the design. The ISE design files provide exact resource use; XPower cross-references routing information with characterized capacitance data. Physical resources are then characterized for capacitance. Design characterization is continuous and ongoing for newer devices to provide the most accurate results. XPower uses net toggle rates as well as output loading. XPower then computes power and junction temperature, and can display individual net power data as well. Conclusion Increasing demands for cheaper and simpler thermal management – as well as power supplies coupled with the increasing power requirements of cutting-edge FPGAs – have elevated the concept of designing for low power to greater heights. The latest device offering from Xilinx, Virtex-4 FPGAs, offers the high performance of 90 nm without the assumed dramatic increase in static power. When used with Xilinx power estimation tools and considerations for low-power design, meeting your power goals is easier than ever. POWER MANAGEMENT Xilinx Events and Tradeshows Xilinx participates in numerous trade shows and events throughout the year. This is a perfect opportunity to meet our silicon and software experts, ask questions, see demonstrations of new products, and hear other customer success stories. For more information and the current schedule, visit www.xilinx.com/events/. Worldwide Events Schedule North America July 12-13 NSREC Seattle, WA Aug. 16-18 National Instruments Week Austin, TX Aug. 23-25 Intel Developer Forum Fall San Francisco, CA Sept. 7-9 MAPLD Washington, D.C. Sept. 13-14 Embedded Systems Conference Boston, MA Oct. 18-20 MILCOM Atlantic City, NJ 50 Xcell Journal Third Quarter 2005
Support Across The Board. National Devices supported: • Voltage Regulators • Voltage Supervisors • Voltage References Xilinx Devices supported: • Virtex • Virtex-E • Virtex-II • Virtex-II Pro • Virtex-4FX, 4LX, 4SX • Spartan-II • Spartan-IIE • Spartan-3, 3E, 3L Power Management Solutions for FPGAs Avnet Electronics Marketing has collaborated with National Semiconductor® and Xilinx® to create a design guide that matches National Semiconductor’s broad portfolio of power solutions to the latest releases of FPGAs from Xilinx. Featuring parametric tables, sample designs and step-by-step directions, this guide is your fast, accurate source for choosing the best National Semiconductor Power Supply Solution for your design. It also provides an overview of the available design tools, including application notes, development software and evaluation kits. Go to em.avnet.com/powermgtguide to request your copy today. Enabling success from the center of technology 1 800 332 8638 www.em.avnet.com © Avnet, Inc. 2005. All rights reserved. AVNET is a registered trademark of Avnet, Inc.
Page 1 and 2: Xcell Issue 54 Third Quarter 2005 j
Page 3 and 4: EDITOR IN CHIEF Carlis Collins edit
Page 5 and 6: THIRD QUARTER 2005, ISSUE 54 Xcell
Page 7 and 8: Hardware Said ... The design flow s
Page 9 and 10: The second idea is to have the hard
Page 11 and 12: and automatic module generation wil
Page 13 and 14: Designing Control Circuits for High
Page 15 and 16: Figure 2 - Implementing an FSM in S
Page 17 and 18: Let’s consider these challenges i
Page 19 and 20: demonstrated by Dr. Howard Johnson,
Page 21 and 22: Pblocks can direct the flow of the
Page 23 and 24: Virtex-4 beats competing FPGAs in e
Page 25 and 26: In addition, you may also use techn
Page 27 and 28: Using Precision Sythesis, Block Mul
Page 29 and 30: 14-Bit, 125Msps ADC Only 395mW Lowe
Page 31 and 32: Non-Symmetric Aspect Ratios/FWFT Ap
Page 33 and 34: QWERTY Building Blocks Our solution
Page 35 and 36: FPGA-Based Video Games Implementing
Page 37 and 38: The Atari 2600 Video Computer Syste
Page 39 and 40: The architecture wizards inside ISE
Page 41 and 42: Smart Telematics Systems from Xilin
Page 43 and 44: interfaces available, Microsoft int
Page 45 and 46: TXPLL TxData[7:0] FIFO an x4 link c
Page 48 and 49: POWER MANAGEMENT Design Techniques
Page 52 and 53: POWER MANAGEMENT Performance vs. Po
Page 54 and 55: POWER MANAGEMENT is the first time
Page 56 and 57: POWER MANAGEMENT Merging CPLD Featu
Page 58: POWER MANAGEMENT A Clear Choice Wit
Page 62 and 63: POWER MANAGEMENT Spartan-3 FPGA Pow
Page 64: POWER MANAGEMENT 5 V_INPUT Highly i
Page 67 and 68: Tool Example Electrical Simulations
Page 69 and 70: y Bill Hargin Product Manager, Hype
Page 71 and 72: Typically used bit patterns, or “
Page 73 and 74: ages and densities for increased fl
Page 75 and 76: see the start sequence, it continue
Page 77 and 78: The Virtex-4 ML450 Development Boar
Page 79 and 80: CONNECTIVITY Bridging System Packet
Page 81 and 82: put stream of SPI-4.2 data. A progr
Page 83 and 84: Controlling Noise A well-designed p
Page 85 and 86: Prototype Your PCIe ASIC HERE See u
Page 87 and 88: knowing what is in R3 of the proces
Page 89 and 90: X-ray X-ray vision vision for for y
Page 91 and 92: The program size is smaller because
Page 93 and 94: Communications) and Verilog PLI, so
Page 95 and 96: Figure 1 - Period constraint in Syn
Page 97 and 98: DEBUGGING Using the actual constrai
Page 99 and 100: Bus Triggering and Display Traditio
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Designer Challenges for Pb-Free and
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A Shortcut to Effective Hierarchica
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Xilinx Education Services: Knowledg
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BIDIR_PAD(7.0) BIDIR this course, w
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Xesium Global Clocking • 500MHz D
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Xilinx Virtex-4 FPGAs www.xilinx.co
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Xilinx CPLD www.xilinx.com/devices/
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Design Example: 1.5 volt LVCMOS 4mA
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Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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