Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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your most pressing design needs. You will learn techniques that may allow you to use a slower speed grade device or fit your design into a smaller device – ultimately saving you money. As you master the tools and design methodologies taught in Designing for Performance, you will be able to create your design faster, with increased performance, shortening your development time and therefore costs. Prerequisites for this course include Fundamentals of FPGA Design and basic VHDL or Verilog knowledge. Designing with the Virtex-4 Family Course At this point, you have taken Fundamentals of FPGA Design and Designing for Performance, but you want to design into the latest and greatest device, the Virtex-4 FPGA. The next course, Designing with the Virtex-4 Family, has an emphasis on teaching you to obtain the highest possible performance (up to 500 MHz internally) and reduce power consumption. This course covers a myriad of new and enhanced capabilities of the Virtex-4 FPGA fabric, with a major emphasis on lab exercises. How do you utilize the new DSP48 resource for arithmetic operations? How do you utilize it for DSP applications? In lab exercises, you will use the DSP48 for DSP and arithmetic applications requiring 500 MHz operation. Did you know that you can also use this resource to implement logic resources such as a 6:1 multiplexer? We will give you the necessary information to take advantage of this dynamic, highperformance, and low-power resource. How would you design a clocking scheme with ten global clocks and six regional clocks? In lab exercises, you will use the new Xesium clocking resources (see Figure 5) to design a complex clocking scheme in Virtex-4 devices. This includes utilizing the enhanced DCM, new phase-matched clock divider (PMCD), enhanced global clock buffers (BUFGCTRL), and new regional clocking resources (BUFIO and BUFR). Have you heard about the block RAM performance enhancements and dedicated FIFO resources? You will create a 500 MHz block RAM core employing the new optional output register. You will also create a core utilizing the new dedicated FIFO16 resources. Do you need to design a source-synchronous interface? The new Virtex-4 IOB tile includes ISERDES and OSERDES resources. You will examine the use of the new Xesium clocking resources and the ISERDES/OSERDES resources for creating your own source-synchronous interface. You will also learn about the available automated tools, ChipSync wizard, and memory interface generator (MIG) for creating source-synchronous interfaces. You will learn to: • Utilize the Xesium global (32) and regional (2 per region) clock networks • Dynamically reconfigure the DCM’s frequency synthesized output (CLKFX) and fine phase shift (DPS) Introduction to VHDL 3 Days ILT Fundametals of FPGA Design 3 Sessions LEL 1 Day ILT Designing for Performance 6 Sessions LEL 2 Days ILT Advanced FPGA Implementation 6 Sessions LEL 2 Days ILT Introduction to Verilog 3 Days ILT • Create phase-matched divided clocks using the new PMCD • Create customized source-synchronous interface cores with the ChipSync wizard or memory interface generator (MIG) • Increase the performance of your memory resources using the new Virtex-4 block RAM and FIFO16 • Increase performance and reduce power of your arithmetic and DSP circuits utilizing the DSP48 resource We are positive that this course will provide the knowledge you need to take full advantage of the performance and power savings offered by the new Virtex-4 FPGA family. The prerequisites for this course include Fundamentals of FPGA Design and Designing for Performance, in addition to intermediate VHDL or Verilog knowledge. Designing with PlanAhead 2 Days ILT * Choose one in this group * Recommended courses: choose one or both Designing with the Virtex-4 Family 2 Days ILT Figure 4 – Curriculum path for FPGA design courses TMR Tool 1 Day ILT * Recommended course Curriculum Path Recommended Course 108 Xcell Journal Third Quarter 2005
Xesium Global Clocking • 500MHz DCM and PMCD • Flexible clock generation • Precise phase control • High-speed differential clocks ChipSync Source Synchronous • Precise delay line bit alignment • SERDES with word alignment • High-speed differential clocks RocketIO High-Speed Serial • >10 Gbps bandwidth with PLL Advanced FPGA Implementation Course Building on the knowledge of the three previous courses, Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE tool suite and Xilinx hardware. This course covers varying topics to help you achieve better results, make changes faster, and maintain your results. Lab exercises are 50% of class time, increasing your knowledge and skills through experimentation. After each small design change, do you get frustrated when you have to completely re-implement a design? Do synthesis and implementation take too long? Do your timing results change? In lab exercises, you will use incremental design techniques (see Figure 3) for an incremental design change, preserving your previous timing results. This can reduce your iterative synthesis and implementation run time by as much as 50%. Are you ready to create an implementation layout? You will use Floorplanner or PACE to create a design layout to increase the performance of your design. Additionally, these tools are used for designs employing incremental design techniques. Do you have a design that uses more than eight clocks? In Virtex-II-based devices, many clocking features are available, but you must also consider their effects. In lab exercises, you will use a simple step-by-step strategy to design a com- Figure 5 – Xesium clocking resources plex multiple-clock clocking scheme in a Virtex-II device, taking advantage of all of the features available. The Virtex-4 clocking resources are also introduced. Are you having trouble meeting timing on a particular path in your design? You will identify when and how to create a relationally placed macro (RPM) for problematic timing paths in your design. An RPM ensures predictable performance results for each included element. In the lab exercise, you will use an RPM to meet performance objectives for a critical path. Do you prefer to use scripts rather than GUIs? With the techniques, strategies, and options covered, you will learn the most effective switches for improving performance. You will also use the settings and options in the scripting lab to greatly improve the performance of the design. You will learn to: • Create and edit timing and placement constraints to increase performance • Build RPMs to improve performance on critical paths and achieve predictable timing results on complex functions • Implement efficient clocking schemes for Virtex-II and Spartan-3 FPGAs • Use incremental design techniques to shorten the design cycle and maintain performance results • Quickly modify implemented designs in FPGA Editor for more efficient incircuit testing • Use scripts and software options to increase performance and reduce area • Use a systematic timing closure strategy to achieve optimum performance With this course, our intent is to arm experienced designers with the necessary techniques, options, and strategies for obtaining breakthrough performance. Once you have achieved your performance objectives, we’ll also teach you how to retain performance from one iteration to the next. Your design goals equate to our teaching objectives. Only the most qualified and experienced instructors and design engineers qualify to teach this class. Instructors tailor the instruction and discussion within the framework of the class to help you achieve your personal learning objectives. This course requires Fundamentals of FPGA Design and Designing for Performance as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended, as is at least six months of design experience with Xilinx FPGAs. Conclusion Our goal is to help you achieve your design goals in the shortest possible time. To do that, we believe we have created the most comprehensive set of courses in the industry to accommodate your complex designs and goals. You can spend days and even weeks trying to accomplish your goals without really learning to quickly, correctly, and strategically use the software and hardware. Rather than waste your time and money, come and learn how the pros do it. For a comprehensive list of training courses available worldwide or to take a skills assessment to find out what courses you need, go to http://xilinx.com/ education, or click on the “Education” link from the support website (the curriculum path for FPGA Design is shown in Figure 4). We truly believe in what we do and what we can help you to do with Xilinx devices. Third Quarter 2005 Xcell Journal 109
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Xcell Issue 54 Third Quarter 2005 j
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EDITOR IN CHIEF Carlis Collins edit
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THIRD QUARTER 2005, ISSUE 54 Xcell
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Hardware Said ... The design flow s
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The second idea is to have the hard
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and automatic module generation wil
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Designing Control Circuits for High
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Figure 2 - Implementing an FSM in S
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Let’s consider these challenges i
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demonstrated by Dr. Howard Johnson,
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Pblocks can direct the flow of the
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Virtex-4 beats competing FPGAs in e
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In addition, you may also use techn
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Using Precision Sythesis, Block Mul
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14-Bit, 125Msps ADC Only 395mW Lowe
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Non-Symmetric Aspect Ratios/FWFT Ap
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QWERTY Building Blocks Our solution
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FPGA-Based Video Games Implementing
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The Atari 2600 Video Computer Syste
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The architecture wizards inside ISE
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Smart Telematics Systems from Xilin
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interfaces available, Microsoft int
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TXPLL TxData[7:0] FIFO an x4 link c
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POWER MANAGEMENT Design Techniques
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Power Estimation Tools Xilinx provi
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POWER MANAGEMENT Performance vs. Po
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POWER MANAGEMENT is the first time
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POWER MANAGEMENT Merging CPLD Featu
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