Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

Pblocks can direct the flow of the
design based on the connectivity of
different modules. The connectivity
of the I/Os to and between modules is
shown for the placed and routed
design through net bundles. We create
Pblocks to cover the critical paths,
which are usually associated with getting
on or off the device.
The schematic view also displays
the connectivity of the design (Figure
2). Pblocks are created either in the
device, schematic, or netlist views.
The critical paths and other timing
paths relative to the existing floorplanning
can be highlighted in the
device and schematic views.
Normally, the schematic view is
used to examine the critical modules
and paths without worrying about the
actual placement of those modules.
The congestion around existing
Pblocks and the resource utilization
of a Pblock are seen in the device
view. If the timing is critical within
the Pblock (indicated by a high
resource utilization count) then we
resize the Pblock to give the congested
logic more room to meet timing by
condensing the logic to shorten the
interconnect lengths and delays. We
can also move the Pblocks to alleviate
congestion or merge congested logic
into a single Pblock.
We create and place the Pblocks, then
run place and route with our floorplanning
constraints. We also lock the locations of the
larger components and critical logic, which
includes block RAMs, DSP48s, and DCMs.
Then we run place and route on the design
and repeat the process by reviewing the timing
report and placement of the design and
modifying the constraints (Figure 2). We
can also create smaller “child” Pblocks inside
other Pblocks to help the grouping of a few
components for timing-critical paths.
Place and route is run on individual
Pblocks in addition to the entire design.
This helps determine if timing can be met
inside the module or Pblock without affecting
the rest of the design. If we are unable
to meet timing on a specific Pblock, we go
back to the source code and re-write it.
Figure 1 – Timing analysis and placement
view of a sample design
Figure 2 – Design connectivity in the
schematic view and timing analysis with
the larger components placed
PlanAhead software can import the
updated netlist for any module and keep
the Pblocks originally created. After meeting
timing requirements, we place location
constraints on all of the elements of that
Pblock. This helps ensure that timing is
retained when the rest of the design is
placed and routed.
The majority of timing failures that we
see are related to setup violations. We also
see hold violations, which are tricky to fix.
Most of the time, a hold violation occurs
because of the placement of critical clocking
components. We get a large number of
clock skew and hold violations when the
DCM and corresponding global buffer are
placed on opposite sides of the device.
PlanAhead software also has a robust set
of DRC checks to highlight these types of
SYSTEM PERFORMANCE
issues early in the flow. We use the
schematic and device views to view
the placement of these components.
We then move the placement of
either the DCM or the global buffer
so that these components are near
each other.
The Design Doesn’t Fit
When a design has difficulty fitting
into the target device, we run it without
any floorplanning constraints.
Usually, overlapping Pblocks exist,
which we remove. We place the large
components manually, as we described
in the previous section, to help the
place and route tools.
If timing is not a critical issue for
this design, we then create Pblocks
of the major hierarchical blocks of
the design. The Pblocks are used to
direct the flow of the design based
on connectivity of the module with
net bundles. The bundles show the
amount of connectivity based on the
size of the bundle. We place the
Pblocks close to the components
that drive them based on the net
bundles and Pblock statistics. We
also place the entire design into a
Pblock and use the compression
attribute on the Pblock(s) to tell
MAP to pack this portion of the
design as tight as possible. This
attribute opens up more room on the rest
of the device for the remaining logic, but
has a negative effect on timing.
We also run place and route on the
individual Pblocks of the design. This
helps ensure that the logic placed in the
Pblocks can be placed and routed within
the defined Pblock size and eventually in
the device specified. We can manually
compress the size of the Pblock until MAP
fails. Once MAP fails, we revert back to
the last known good size of the Pblock.
The statistics of the Pblock may
report that we used more than 100%,
but MAP will determine if it passes. We
repeat this process if other non-timing
critical Pblocks exist and use the compression
attribute to pack those Pblocks
as tight as possible.
Third Quarter 2005 Xcell Journal 21