Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

DEBUGGING
Using the actual constraint of 190 MHz decreased design
performance after implementation from 189 MHz to 180 MHz.
Floorplanner
With the help of Xilinx Floorplanner, we
can determine the connectivity of “s_”. In
Figure 2, “s_” is selected (yellow). The
black lines represent its connectivity in
relation to the other parts of the design.
This instance is spread out, so an area
group constraint is necessary. Instead of
entering the area group constraint into a
UCF, we entered the constraint SCOPE,
which allows the Synplify tool to make
timing decisions based off the physical
placement of the logic. In fact, we achieved
worse results when we entered the constraints
directly into a UCF file (bypassing
the synthesis tool).
Area Groups
You can enter the area group constraint
through SCOPE by selecting the attributes
tab. Each cell in SCOPE has a pull-down
menu with only the correct values available.
As shown in Figure 3, the “s_”
instance is found and the xc_area_group
constraint is selected.
After several iterations, we found a good
area group constraint that worked well with
ISE software, producing a minimum period
of 187 MHz. We continued this iterative
process, trying area groups on different
instances as well as trying different PAR cost
tables (a PAR cost table gives a different starting
point for the place and route process).
Ultimately, we placed area group constraints
on two instances inside of “s_” and
Figure 3 – Area group constraint
used a PAR cost table setting of 8 to get the
final minimum period of 189 MHz, close
to the arbitrary goal of 190 MHz and a significant
improvement over the unconstrained
design speed of 115 MHz.
As a final confession, we used the NCF
period constraint of 220 MHz. Using the
actual constraint of 190 MHz decreased
design performance after implementation
from 189 MHz to 180 MHz. This is
not normal behavior from PAR. Overconstraining
in PAR can have the same
detrimental results as over-constraining
in synthesis, so a design with a positive
effect of an over-constrained period in
PAR represents a corner case.
Conclusion
Our design was small and easily fit in the
smallest Spartan-3 device. However,
using the same methodologies outlined in
this article, a significantly larger design
can meet timing using Synplify Pro’s constraints
and switches and passing those
constraints to ISE software.
Using the switches in Synplify
Pro software, SCOPE, and Xilinx
Floorplanner, our design met the arbitrary
goal and a significant timing closure
on a Spartan-3 design.
For more information, visit www.
synplicity.com/products/synplifypro/index.htm
l and www.xilinx.com/spartan3.
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96 Xcell Journal Third Quarter 2005
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