Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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CONNECTIVITY Virtex-4 Source-Synchronous Interfaces Tool Kit The Virtex-4 ML450 Source-Synchronous Interfaces Tool Kit provides a complete development platform for designing and verifying applications based on the Virtex-4 LX FPGA family. by David Naylor Sr. Product Applications Engineer Xilinx, Inc. david.naylor@xilinx.com Many of today’s telecom and networking systems use high-bandwidth interfaces based on low voltage differential signaling (LVDS) or other differential I/O standards. Differential I/O standards simplify system design by improving system performance and signal integrity. Protocols based on I/Os such as SPI-4.2, SFI, RapidIO, and HyperTransport are central to leading-edge system design. To take advantage of these technologies, you have to work through multiple challenges to ensure device interoperability and standards compliance. Xilinx ® provides Virtex-4 development boards as well as standards-compliant intellectual property (IP) cores and free reference designs for major system interface protocols. This allows you to focus on user application design and not worry about interoperability and standards compliance. With the Virtex-4 source-synchronous interfaces tool kit, designing networking, telecom, servers, and computing systems has never been faster or easier. The Virtex-4 ML450 source-synchronous interfaces tool kit includes the following: • Virtex-4 ML450 development board (XC4VLX25FF668 FPGA) • 5V/6.5 AC/DC power supply • Country-specific power supply line cord • RS232 serial cable, DB9-F to DB9-F • Four clock module daughter boards • Two sets of “blue ribbon” loopback cables for LVDS testing • Documentation and reference design CD-ROM 76 Xcell Journal Third Quarter 2005
The Virtex-4 ML450 Development Board The main component in the Virtex-4 ML450 source-synchronous interfaces tool kit is the ML450 development board (Figure 1). Featuring a Virtex-4 XC4VLX25FF668 FPGA coupled to highspeed connectors, this board supports the development of high-speed interface designs using several popular protocols. The ML450 demonstration board is a simple board providing several connector interfaces to the FPGA. The board comprises basic support circuitry, including power regulators, a serial RS232 connector, a small graphics LCD, a few user push buttons and LEDs, and a DDR-1 SDRAM. These simple peripherals allow a PC to communicate with the FPGA and also provide basic input and output indicators. Configuration is enabled via a JTAG connector, or you can use a System ACE CompactFlash card for bitstream storage and loading. We designed the board to demonstrate the high-speed I/O capability of the Virtex-4 FPGA. Eighty differential channels are pinned out to four Samtec connectors. Forty pairs each are routed to two connectors on either side of the FPGA, allowing you to designate “transmit” and “receive” interfaces. Two “mini coax” flat cables are provided with the kit, enabling loopback of high-speed data between transmit and receive connectors. In addition to these differential signals, another 32 pairs are routed to a HyperTransport Consortium DUT (device under test)-compliant connector, allowing for the development of an interface to other HyperTransport-based boards. The ML450 evaluation platform supports a wide range of communications standards, including SFI-4. Figure 2 shows the user interface of an SFI-4 demo running on an ML450 board. The user interface includes a bit error rate tester (BERT) that measures the integrity of the data received from 16 LVDS transmitters. You can select from several pseudo-random bit sequences to simulate data, and error counters on the user interface maintain a running count of all bit errors that occur during transmission. The BERT also keeps track of which channels are receiving errors to provide further troubleshooting visibility in a multi-channel design. 64 MByte SDRAM Oscillators 200 and 250 MHz Differential Clock Inputs (2 Sets SMA) Clock Module (4 Locations) Clock Generator RS-232 Port LCD Panel User Switches User LEDs In terms of performance, the ML450 platform supports a 16-channel single data rate design (SDR) running up to 700 MHz (Figure 3) and a 16-channel double data rate (DDR) design running up to 500 MHz (Figure 4). The transmission medium of the 16 channels consists of two Samtec connectors, a 12-inch ribbon cable, and 10 inches of FR4. The ML450 also provides the ability to command the supply rails of the FPGA to assume ±5% of their nominal values. This feature provides a convenient way for you to stress your design and identify marginal behavior. The voltages are controlled through the user interface by simply moving a slider button to the left or right. In Figure 2, VccAux is raised to +5%, while the other supplies remain nominal. A small daughtercard that plugs onto the board provides the high-speed clock used by the SFI-4 design. This daughtercard generates a programmable LVDS clock between 200 MHz and 700 MHz, Virtex-4 FPGA XC4VLX25 (FF668) CONNECTIVITY eliminating the need for a cumbersome bench-top pulse generator. Board Features The ML450 development board includes the following: • XC4VLX25FF668 FPGA • Eight clock sources: System ACE Module Mezzanine Board Connector HyperTransport Connector LVDS Receive Connector LVDS Transmit Connector Parallel Cable IV JTAG Port JTAG Port System 3.3V System 2.6V VCCAUX 2.5V V CCO 2.5V V CCINT 1.2V Voltage Regulators Figure 1 – Virtex-4 ML450 networking interfaces development board – 200 MHz and 250 MHz on-board oscillators – Two sets of SMA differential clock input connectors – Four Samtec clock module connectors • One 64 x 128 pixel LCD • One DB9-M RS232 port • A System ACE CompactFlash configuration controller that allows storing and downloading of as many as eight FPGA configuration image files Third Quarter 2005 Xcell Journal 77
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Xcell Issue 54 Third Quarter 2005 j
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Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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