Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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Introducing the new Spartan-3E family — the world’s lowest-cost FPGAs Priced to go. Pb-free devices available now The industry’s first 100,000-gate FPGA for only $2.00* Spartan-3E Platform FPGAs offer an amazing feature set for just $2.00! You get 100K gates, embedded multipliers for high-performance/low-cost DSP, plenty of RAM, digital clock managers, and all the I/O support you need. All this in a production-proven 90nm FPGA with a density range up to 1.6 million gates. Perfect for digital consumer apps and much more! With the Spartan-3E series, we’ve reduced the previous unit cost benchmark by over 30%. Optimized for gate-centric designs, and offering the lowest cost per logic cell in the industry, Spartan-3E FPGAs make it easy to replace your ASIC with a more flexible, faster-to-market solution. Compare the value for yourself . . . and get going on your latest design! * Pricing for 500K units, second half of 2006 MAKE IT YOUR ASIC The Programmable Logic Company SM For more information visit www.xilinx.com/spartan3e ©2005 Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Europe +44-870-7350-600; Japan +81-3-5321-7711; Asia Pacific +852-2-424-5200; Xilinx is a registered trademark, and The Programmable Logic Company is a service mark of Xilinx, Inc.
EDITOR IN CHIEF Carlis Collins editor@xilinx.com 408-879-4519 MANAGING EDITOR Forrest Couch forrest.couch@xilinx.com 408-879-5270 ASSISTANT MANAGING EDITOR Charmaine Cooper Hussain XCELL ONLINE EDITOR Tom Pyles tom.pyles@xilinx.com 720-652-3883 ADVERTISING SALES Dan Teie 1-800-493-5551 ART DIRECTOR Scott Blair Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124-3400 Phone: 408-559-7778 FAX: 408-879-4780 www.xilinx.com/xcell/ © 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx Logo, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. The articles, information, and other materials included in this issue are provided solely for the convenience of our readers. Xilinx makes no warranties, express, implied, statutory, or otherwise, and accepts no liability with respect to any such articles, information, or other materials or their use, and any use thereof is solely at the risk of the user. Any person or entity using such information in any way releases and waives any claim it might have against Xilinx for any loss, damage, or expense caused thereby. L E T T E R F R O M T H E E D I T O R Life’s Challenges: Opportunity or Curse? L“Life is full of challenges.” You have probably heard this thought often. But how often have you really used challenges to learn more about yourself and grow from the experience? You probably view challenges as unwelcome speed bumps on the road to success and happiness. But are they really? My personal experience has shown that challenges are tremendous opportunities for moving to the next level. Whether personal, professional, or otherwise, challenges can reveal your blind spots, provide the motivation for making a change, and show you where you need to make necessary changes and grow. At Xilinx ®, we are very aware of the design challenges facing today’s system designers. Accordingly, we are constantly looking to see what and how we need to change to keep up with market demands. We also realize that we too may have a few blind spots, so we are continually asking our market for suggestions on how to improve. This issue of the Xcell Journal focuses on design challenges, comprising articles on system performance, total cost, power management, connectivity, and debug. To highlight just a few, Adrian Cosoroaba’s article, “Achieve Breakthrough Performance in Your System,” discusses how Virtex-4 FPGAs set new records in system performance while consuming minimal power and providing superior signal integrity. For reducing total cost, there are several articles illustrating examples of low-cost system implementations. They include using a CPLD to implement a QWERTY keypad; implementing video games in FPGAs; using Xilinx ISE 7 design tools to get the most out of your silicon while slashing project costs; staying connected while driving safely using advanced telematics; and a low-cost programmable PCI Express solution. In Anil Telikepalli’s power management article, “Performance vs. Power: Getting the Best of Both Worlds,” he discusses the fact that excessive power is expensive in many ways. Excessive power creates the need for special design and operational considerations – everything from heat sinks to fans to sophisticated heat exchangers. Even the cost of larger power supplies must be considered. In the connectivity article “Bridging System Packet Interfaces,” co-authored by several Xilinx engineers from the IP Solutions Division, Xilinx IP and reference designs provide superior solutions for implementing custom bridging solutions between protocols. This article discusses the benefits and utility of the SPI-4.2 to Quad SPI-3 Bridge, which demonstrates how to bridge four SPI-3 cores to a single SPI-4.2 core. And finally, Ross Nelson’s debug article, “Hardware/Software Co-Verification,” discusses how to gain full visibility into your software and hardware and achieve a faster design iteration loop in the process. We hope you enjoy this issue on design challenges. And remember: life is full of challenges, but perception is everything. Forrest Couch Managing Editor
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Page 7 and 8: Hardware Said ... The design flow s
Page 9 and 10: The second idea is to have the hard
Page 11 and 12: and automatic module generation wil
Page 13 and 14: Designing Control Circuits for High
Page 15 and 16: Figure 2 - Implementing an FSM in S
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Page 21 and 22: Pblocks can direct the flow of the
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Page 25 and 26: In addition, you may also use techn
Page 27 and 28: Using Precision Sythesis, Block Mul
Page 29 and 30: 14-Bit, 125Msps ADC Only 395mW Lowe
Page 31 and 32: Non-Symmetric Aspect Ratios/FWFT Ap
Page 33 and 34: QWERTY Building Blocks Our solution
Page 35 and 36: FPGA-Based Video Games Implementing
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Page 41 and 42: Smart Telematics Systems from Xilin
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POWER MANAGEMENT Performance vs. Po
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POWER MANAGEMENT is the first time
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POWER MANAGEMENT Merging CPLD Featu
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POWER MANAGEMENT A Clear Choice Wit
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POWER MANAGEMENT Spartan-3 FPGA Pow
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POWER MANAGEMENT 5 V_INPUT Highly i
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Tool Example Electrical Simulations
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ages and densities for increased fl
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see the start sequence, it continue
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The Virtex-4 ML450 Development Boar
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CONNECTIVITY Bridging System Packet
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put stream of SPI-4.2 data. A progr
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Controlling Noise A well-designed p
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Prototype Your PCIe ASIC HERE See u
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knowing what is in R3 of the proces
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X-ray X-ray vision vision for for y
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The program size is smaller because
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Figure 1 - Period constraint in Syn
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DEBUGGING Using the actual constrai
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Bus Triggering and Display Traditio
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Designer Challenges for Pb-Free and
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A Shortcut to Effective Hierarchica
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Xilinx Education Services: Knowledg
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BIDIR_PAD(7.0) BIDIR this course, w
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Xesium Global Clocking • 500MHz D
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Xilinx Virtex-4 FPGAs www.xilinx.co
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Xilinx CPLD www.xilinx.com/devices/
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Design Example: 1.5 volt LVCMOS 4mA
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Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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