Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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$ TOTAL COST Using a CPLD to Implement a QWERTY Keypad You can use a Xilinx CPLD to expand a typical handset DTMF keypad into a QWERTY keypad. by Mike Gulotta Xilinx FAE Xilinx, Inc. mike.gulotta@xilinx.com As cell phones and other portable handheld devices continue to add features, design trade-offs are constantly evolving. Popular features such as text messaging and web browsing demand more data entry, but that can be cumbersome with traditional dual tone multiple frequency (DTMF) (0-9, #, *) keypads. Using this type of keypad requires multi-tap data entry, which is inefficient and error-prone. One option to make text entry easier is to use a QWERTY keypad (Figure 1). This type of keypad employs 40 or more keys versus the normal 12 in a DTMF handset, although the additional keys make the handset larger and involve more electronic components. Text message users may be willing to trade size for a QWERTY keypad; text entry is much easier and you can use two thumbs to enter text messages or data. Recently, some cell phone manufacturers have released handsets with QWERTY keypads that cater to text users. There are many ways to design data entry keypads, but no standard exists. In this article, we’ll examine one possible solution to the design challenge of adding additional keys to a traditional DTMF-type keypad. 32 Xcell Journal Third Quarter 2005
QWERTY Building Blocks Our solution uses a Xilinx ® CoolRunner-II CPLD; its low power, small package options, and low cost make it an ideal candidate for this application. Going from a DTMF to a QWERTY keypad requires more keys and thus more general-purpose I/O (GPIO). For instance, a DTMF keypad may have only four rows and three columns, whereas a QWERTY keypad may have as many as Figure 1 – QWERTY keypad (Motorola model A630) eight rows and eight columns. But keypad size can vary depending on the requirements of the end system. Typically, a processor or DSP is used as an interface to the keypad’s rows and columns (see Figure 2). The processor scans the rows and monitors the columns for a logic change. When a change occurs, it indicates that the user pressed one of the buttons. By knowing which row was being scanned and which column changed state, the processor can deduce which specific button was pushed. Expanding I/O When designing keypads that require more I/O (as is the case with a QWERTY keypad), you may find that your existing processor does not have enough GPIO. A possible solution is to use a CPLD as an I/O expander to reduce the number of I/Os required from the processor. Figure 3 introduces a CPLD in between the processor and keypad where one side of the CPLD interfaces to the keypad rows/columns and the other side interfaces to the processor’s available GPIO. In this example, an 8 x 8 keypad requires the same number of processor GPIO ports as the 4 x 4 keypad (actually one less) when using a CPLD. Without the CPLD, the processor would require 16 GPIO ports instead of 7. Scanning and Encoding In addition to reducing the processor’s GPIO requirements, the CPLD can offload some of the processor functions, such as scanning the rows and monitoring the columns for a change in state. When the user presses a key, the CPLD stops scanning and immediately produces an encoded word, which is sent to the processor. The encoded word lets the processor know which key was pressed. This will reduce processor I/O requirements because an encoded word is used to convey which button is pressed to the processor. In the example shown in Figure 3, six bits are used to rep- Processor GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 resent the encoded word. Six bits provide 2 6 or 64 different values, each representing a different key. However, one value must represent the state when no keys are pressed. So really, only 63 keys can be represented in this example (without adding an additional GPIO). The processor does not need to scan the keypad because this is being performed by the CPLD; however the processor is still required to monitor for changes on its GPIO – only it would not need to deduce which key was pressed because the information is encoded in a six-bit word. Switch debounce is also needed. It can be designed in the CPLD or the processor, depending on which device has available resources. Performing this in the processor will keep the size and cost of the CPLD to a minimum. Summarizing this design example, the CPLD scans the keypad for a pressed key and provides an encoded word to the processor to read and interpret. This function not only offloads the processor from scanning but expands the GPIO. 4 x 4 Keypad Third Quarter 2005 Xcell Journal 33 row0 row1 row3 row3 col0 col1 col2 col3 Figure 2 – Simple 4 x 4 keypad connected to a processor requiring eight GPIO $ TOTAL COST
Page 1 and 2: Xcell Issue 54 Third Quarter 2005 j
Page 3 and 4: EDITOR IN CHIEF Carlis Collins edit
Page 5 and 6: THIRD QUARTER 2005, ISSUE 54 Xcell
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Page 9 and 10: The second idea is to have the hard
Page 11 and 12: and automatic module generation wil
Page 13 and 14: Designing Control Circuits for High
Page 15 and 16: Figure 2 - Implementing an FSM in S
Page 17 and 18: Let’s consider these challenges i
Page 19 and 20: demonstrated by Dr. Howard Johnson,
Page 21 and 22: Pblocks can direct the flow of the
Page 23 and 24: Virtex-4 beats competing FPGAs in e
Page 25 and 26: In addition, you may also use techn
Page 27 and 28: Using Precision Sythesis, Block Mul
Page 29 and 30: 14-Bit, 125Msps ADC Only 395mW Lowe
Page 31: Non-Symmetric Aspect Ratios/FWFT Ap
Page 35 and 36: FPGA-Based Video Games Implementing
Page 37 and 38: The Atari 2600 Video Computer Syste
Page 39 and 40: The architecture wizards inside ISE
Page 41 and 42: Smart Telematics Systems from Xilin
Page 43 and 44: interfaces available, Microsoft int
Page 45 and 46: TXPLL TxData[7:0] FIFO an x4 link c
Page 48 and 49: POWER MANAGEMENT Design Techniques
Page 50 and 51: Power Estimation Tools Xilinx provi
Page 52 and 53: POWER MANAGEMENT Performance vs. Po
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Page 56 and 57: POWER MANAGEMENT Merging CPLD Featu
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Controlling Noise A well-designed p
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Figure 1 - Period constraint in Syn
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DEBUGGING Using the actual constrai
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Bus Triggering and Display Traditio
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Designer Challenges for Pb-Free and
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A Shortcut to Effective Hierarchica
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Xilinx Education Services: Knowledg
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BIDIR_PAD(7.0) BIDIR this course, w
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Xesium Global Clocking • 500MHz D
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Xilinx Virtex-4 FPGAs www.xilinx.co
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Xilinx CPLD www.xilinx.com/devices/
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Design Example: 1.5 volt LVCMOS 4mA
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Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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