Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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POWER MANAGEMENT Performance vs. Power: Getting the Best of Both Worlds Xilinx conquers the 90 nm inflection point. by Anil Telikepalli Marketing Manager, Virtex Solutions Xilinx, Inc. anil.telikepalli@xilinx.com The debate over which high-performance 90 nm FPGA has the lowest power is heating up. The industry has crossed a critical inflection point at the 90 nm process, where performance competes with power and thermal budgets. Customers want as much performance as possible, but increasingly the decision about which FPGA to use is based on which device consumes the least amount of power. Excessive power is expensive in many ways. It creates the need for special design and operational considerations – everything from heat sinks to fans to sophisticated heat exchangers. Even the cost of larger power supplies must be considered. Perhaps the most critical issue is the effect excessive power can have on reliability. As junction temperatures rise, transistors consume more power, further increasing the device temperature. Left unchecked, this phenomenon leads to thermal runaway. Continuously operating systems with junction temperatures from 85°C to over 100°C threaten the reliability of the device. 52 Xcell Journal Third Quarter 2005
Normalized Power 500 100 1 0.01 0.0001 Static Power Significant at 90 nm 350 250 180 130 90 65 45 22 Static Power (leakage) 0.0000001 1990 1995 2000 2005 2010 2015 2020 Fortunately, Xilinx ® encountered the first evidence of this 90 nm inflection point more than three years ago, in the early development stages of Spartan-3 FPGAs (the first Xilinx FPGA family with the 90 nm process). Xilinx began immediately developing new ways to cope with the inherent power issues posed by the 90 nm process. Consequently, when the higher performance Virtex-4 family was introduced in September 2004, Xilinx was confident that the new family would simultaneously deliver the highest performance and lowest power consumption in a 90 nm FPGA. Reducing Power in FPGAs There are two major components to power consumption: static power and dynamic power. Each component poses a unique challenge. For the 90 nm FPGA, the most challenging component is static power. Static Power Static power is the standby power that is wasted even if the design is not performing any function. It occurs as a result of leakage current in the transistors within the FPGA. Leakage current increases as transistors get smaller with each new process. This principle is one of the major reasons the 90 nm process crosses a major inflection point (Figure 1). Dynamic Power Figure 1 – The 90 nm inflection point Technology Node (nm) International Technology Roadmap for Semiconductors (ITRS) 2001, 2002. Courtesy: Moore's Law Meets Static Power, Computer, December 2003. IEEE Computer Society For the first time, static power is threatening to eclipse dynamic power as the component responsible for the greatest amount of total power consumption in an FPGA. As processes get smaller, core voltage decreases and parasitic capacitance decreases; consequently, the rate of increase in dynamic power drops, despite the increase in frequency that accompanies a new process. In contrast, below 0.25 µms static power has grown exponentially with each new process. This is where the inflection point really becomes a critical factor for the FPGAs and where Xilinx has established a substantial lead. Smaller transistors are faster, Relative Static Power (Worst Case Process @ 85oC) 6 5 4 3 2 1 0 XC2VP20 0 25K XC4VLX25 Virtex-II Pro but they leak more. Thicker gate oxides reduce leakage, but they also reduce performance. However, unlike ASICs, ASSPs, and microprocessors, Xilinx FPGAs do not need all of their transistors to switch at maximum speed. A substantial number of transistors make up the configuration memory cells used for programmable logic, while pass transistors are used to implement the programmable interconnect routing. Configuration memory cells do not need to be fast, and programmable interconnect transistors only need to be fast from source to drain and not under gate control. These factors have allowed Xilinx to selectively increase gate-oxide thickness to reduce leakage current without compromising performance. Virtex-4 FPGAs incorporate a new process approach called triple-oxide technology to solve the static power problem. Although this third gate-oxide layer is still very thin, these transistors exhibit substantially lower leakage than the standard thin-oxide transistors used in Virtex-II Pro FPGAs and in various other parts of Virtex-4 FPGAs. In addition, Xilinx optimized a number of other transistor parameters (including V T) to balance performance and leakage across I/O, configuration memory, interconnect pass transistors, and logic and interconnect buffers. Figure 2 shows that Virtex-4 FPGAs consume 50% less static power than their predecessor, 130 nm Virtex-II Pro FPGAs. We believe that this XC2VP100 XC4VLX200 XC4VLX100 50K 75K 100K Logic Cells POWER MANAGEMENT 50% Lower Power Virtex-4 125K 150K 175K 200K Figure 2 – The use of “triple-oxide” technology reverses the trend: the Virtex-4 device actually consumes less static power than its 130 nm predecessor. Third Quarter 2005 Xcell Journal 53
Page 1 and 2: Xcell Issue 54 Third Quarter 2005 j
Page 3 and 4: EDITOR IN CHIEF Carlis Collins edit
Page 5 and 6: THIRD QUARTER 2005, ISSUE 54 Xcell
Page 7 and 8: Hardware Said ... The design flow s
Page 9 and 10: The second idea is to have the hard
Page 11 and 12: and automatic module generation wil
Page 13 and 14: Designing Control Circuits for High
Page 15 and 16: Figure 2 - Implementing an FSM in S
Page 17 and 18: Let’s consider these challenges i
Page 19 and 20: demonstrated by Dr. Howard Johnson,
Page 21 and 22: Pblocks can direct the flow of the
Page 23 and 24: Virtex-4 beats competing FPGAs in e
Page 25 and 26: In addition, you may also use techn
Page 27 and 28: Using Precision Sythesis, Block Mul
Page 29 and 30: 14-Bit, 125Msps ADC Only 395mW Lowe
Page 31 and 32: Non-Symmetric Aspect Ratios/FWFT Ap
Page 33 and 34: QWERTY Building Blocks Our solution
Page 35 and 36: FPGA-Based Video Games Implementing
Page 37 and 38: The Atari 2600 Video Computer Syste
Page 39 and 40: The architecture wizards inside ISE
Page 41 and 42: Smart Telematics Systems from Xilin
Page 43 and 44: interfaces available, Microsoft int
Page 45 and 46: TXPLL TxData[7:0] FIFO an x4 link c
Page 48 and 49: POWER MANAGEMENT Design Techniques
Page 50 and 51: Power Estimation Tools Xilinx provi
Page 54 and 55: POWER MANAGEMENT is the first time
Page 56 and 57: POWER MANAGEMENT Merging CPLD Featu
Page 58: POWER MANAGEMENT A Clear Choice Wit
Page 62 and 63: POWER MANAGEMENT Spartan-3 FPGA Pow
Page 64: POWER MANAGEMENT 5 V_INPUT Highly i
Page 67 and 68: Tool Example Electrical Simulations
Page 69 and 70: y Bill Hargin Product Manager, Hype
Page 71 and 72: Typically used bit patterns, or “
Page 73 and 74: ages and densities for increased fl
Page 75 and 76: see the start sequence, it continue
Page 77 and 78: The Virtex-4 ML450 Development Boar
Page 79 and 80: CONNECTIVITY Bridging System Packet
Page 81 and 82: put stream of SPI-4.2 data. A progr
Page 83 and 84: Controlling Noise A well-designed p
Page 85 and 86: Prototype Your PCIe ASIC HERE See u
Page 87 and 88: knowing what is in R3 of the proces
Page 89 and 90: X-ray X-ray vision vision for for y
Page 91 and 92: The program size is smaller because
Page 93 and 94: Communications) and Verilog PLI, so
Page 95 and 96: Figure 1 - Period constraint in Syn
Page 97 and 98: DEBUGGING Using the actual constrai
Page 99 and 100: Bus Triggering and Display Traditio
Page 101 and 102: Designer Challenges for Pb-Free and
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A Shortcut to Effective Hierarchica
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Xilinx Education Services: Knowledg
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BIDIR_PAD(7.0) BIDIR this course, w
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Xesium Global Clocking • 500MHz D
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Xilinx Virtex-4 FPGAs www.xilinx.co
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Xilinx CPLD www.xilinx.com/devices/
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Design Example: 1.5 volt LVCMOS 4mA
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