Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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$ TOTAL COST A Flexible and Scalable Platform The traditional automotive electronic design approach has been to develop very specific, tailored, and rigid solutions based on the needs of automotive manufacturers. Telematics and infotainment are forcing the automotive industry to rethink the products and systems designed into a typical “connected car.” The convergence of the consumer world into the vehicle – in applications such has telematics – has forced “consumer development” thinking into an industry that is traditionally slow, conservative, and cost driven. New requirements carried across from the consumer industry demand rapid change, as consumers always expect to have the next big thing. This demand is forcing the need for flexible architectures and changes to design methodology that can cope with not only current applications but future and possibly unknown features. This conflicts with the multi-year development and validation cycles that typical automotive electronic designs generally require. It is now essential that a platform developed today (for a vehicle to be released in two to three years) has sufficient system resources to cope with unexpected changes both throughout the product development cycle and after introduction. As with any platform, flexibility and scalability are key to the successful adoption of the architecture, from basic systems through to high-performance, high-end telematics systems. With this in mind, Microsoft has developed a true automotive standard telematics platform that is customizable and scalable. The platform incorporates an ARM 9based microcontroller, supports memory from 32 MB flash/32 MB DRAM upwards, and includes integrated GPS Bluetooth and a GSM phone module. External vehicle connections include a CAN network interface as well as protected analog and digital I/O for functions such as LED drivers and button inputs. The basic architecture of the platform is shown in Figure 1. Microsoft took advantage of the flexibility and high integration possibilities of FPGA technology. A Spartan-3 XC3S400 FPGA was used in this platform for multiple independent purposes such as a GSM phone interface, vehicle interfaces (CAN controller and K-line), and sophisticated audio signal conditioning and routing (shown in Figure 2). The high levels of integration that FPGAs offer also have the advantage of I2S D_IN Memory Card Color Graphic LCD Analog and Discrete I/O Processor Local Bus I2S D_OUT CPU Codec_clk (256 fs) UPLL_clk up_uclk NAND Flash 32-512 MB Serial Debug Phone Interface FULL UART “0” 12288 KHz UART Clock 48 MHz Clock Generator FPGA System Clock 14.769 MHz K-Line Misc. I/O Bus Interface LEDs, Etc. I/O 4-way MUX FPGA Registers t Mini- UART containing multiple buses, interfaces, and clocks within one device, making design with EMI more manageable. In addition, reducing component count and board space leads to lower production costs and a higher quality of manufacture – important factors in any automotive design. Understanding the nature of vehicle development and the multitude of vehicle FPGA Block Diagram 42 Xcell Journal Third Quarter 2005 I2S Decoder L R XC3S400-FT256 CLK_24 To CAN SDRAM 32-512 MB 32-bit LPB JTAG Debug NAND Memory JTAG IF USB Mont USB Mont MMC150 USB Divide LCD cfm CPU 300-400 MHz CS AJD and GPIO UART UART UART Bluetooth GPS PC1 B_cs C_cs C3-cs rd_n wr_n ale CAN Controller Interface State Machine Acoustic Echo Cancellation Noise Reduction PCM Encoder JTAG FPGA 200K-400K Gates PCM uF USB Flash Drive USB Debug Speech FIFO (DMA) 1024 x 16 “0” PCMFR PCMCLK PCMRX PCMTX BLUETOOTH 18-bit 2 125 mF UART CAN “0” Gain X 6 PCM Decoder “0” 3 SIM Socket Cellphone Module Data/Voice L R L R S “0” PCMTX PCMRX GSM I2S Decoder L R PCM uF I2S Encoder CMS Voice In CMS Voice Out Stereo CODEC Line Out TLV320AIC Mic In Figure 1 – Microsoft telematics platform hardware architecture Figure 2 – Xilinx Spartan-3 FPGA design Mono CODEC CODEC I2S_TX CODEC I2S_RX
interfaces available, Microsoft intentionally designed a flexible solution that allows rapid changes to the back-end vehicle interface without affecting the underlying architecture and performance of the system. For example, in the future it would be possible to adapt the FPGA solution to suit the needs of the end application with automotive buses such as MOST, IDB-1394, or another digital vehicle network. Voice Recognition System Central to the Microsoft Telematics Platform is the voice recognition (VR) system. The audio signal path within any VR system is analog biasing/filtering, digitization, and digital filtering before the signal is finally presented to the VR engine for speech processing. Within this path, multiple opportunities exist for unwanted noise to be introduced into the system (both onboard the electrical platform and within the vehicle environment even before the electronics). Both the product developer and the vehicle manufacturer must ensure that the microphone position and type are correctly suited to the application and environment. In a perfect world, the VR engine will receive clean, consistent speech signals – but given the dynamic nature of the vehicle environment, acceptable voice recognition implementation is not a straightforward exercise. Factors such as vehicle speed, window position (open/closed), road noise, and weather conditions (rain/wind) only add to already difficult VR problems such as languages, accents, and gender. These added factors have increased the importance of preconditioning using highly adaptive digital filtering algorithms before the signal is presented to the VR engine. Microsoft chose to implement this signal preconditioning in hardware and take advantage of Xilinx parallel DSP processing. Spartan-3 FPGAs, with as many as 104 embedded 18-bit multipliers, are ideal for implementing compact DSP structures such as MAC engines, distributed arithmetic FIR filters, and fully parallel FIR filters in a low-cost device. Microsoft also offloaded processorintensive software filtering into hardware. Of course, this pre-processing is possible in ASSPs such as dedicated DSP chips. But the benefits gained through high levels of integration in other parts of the platform would be lost. The combination of telematics and VR allows implementations of adaptable and upgradeable VR engines and DSP filters tailored to suit certain types of users and environments (Language: English, Accent: Scottish, Gender: Female). The importance of designing automotive products (especially in the infotainment section of the vehicle) with sufficient spare bandwidth to cope with new and unexpected future upgrades also applies to the FPGA. It is now becoming clear to automotive OEMs that architectures that allow for flexible and scalable firmware are a necessity in future platforms. Although not currently implemented in the Microsoft platform, it would be possible to easily add soft processors to act as system co-processors. Just as the DSP processing was offloaded from the main processor in Microsoft’s design, it would also be possible to use embedded processors (such as the Xilinx 32-bit MicroBlaze soft processor or 8-bit PicoBlaze microcontrollers) to take some of the processing load from the main system processor. FPGAs for Automotive Applications In-car electronics have seen tremendous growth in recent years, not only in traditional body control and engine management but in the new areas of driver assistance systems and telematics applications. Figures recently published by the IEEE indicated an annual increase in car electronics of 16%, with a prediction that by 2005 electronics will account for 25% of the cost of a mid-size car. Telematics systems exhibit characteristics more like those of consumer products – short time to market, short time in market, and changing standards and protocols. These issues impact the way engineers approach designs and select the hardware needed to quickly create, iterate, and support future upgrading. FPGA technology can now solve these requirements. Xilinx is committed to serving telematics and car infotainment applications through its Xilinx Automotive (XA) family, which delivers: • Extended temperature ranges – up to 125°C • Full production part approval process (PPAP) support • Industry-recognized AEC-Q100 devicequalification flow • Compliance with the worldwide automotive quality standard ISO TS 16949, as well as Pb-free packaging to meet the RoHS directive These devices, based on our Spartan family of FPGAs, are ideal for digital designs requiring low cost per logic cell (system gate), low cost per I/O, and advanced features such as multiple I/O standards on a singe device and embedded multipliers for high-speed DSP. Conclusion Backed by a commitment from supporters such as the Microsoft Automotive Business Unit and Xilinx Automotive, the vision of Microsoft’s Telematics Platform is now becoming a reality. The convergence of key technologies is being adopted today by first-tier automobile manufacturers in a platform that enables: • A valuable and affordable telematics solution • Reliable connectivity through wireless networks • High-quality voice recognition • A broadly supported operating system for application developers • Low-cost hardware This is giving rise to a “virtuous cycle” of continuous investment by developers, who will use these platforms to create even more value for end users. For more information, visit www.microsoft.com/automotive/ windowsautomotive/about.mspx/ and www. xilinx.com/automotive/. Third Quarter 2005 Xcell Journal 43 $ TOTAL COST
Page 1 and 2: Xcell Issue 54 Third Quarter 2005 j
Page 3 and 4: EDITOR IN CHIEF Carlis Collins edit
Page 5 and 6: THIRD QUARTER 2005, ISSUE 54 Xcell
Page 7 and 8: Hardware Said ... The design flow s
Page 9 and 10: The second idea is to have the hard
Page 11 and 12: and automatic module generation wil
Page 13 and 14: Designing Control Circuits for High
Page 15 and 16: Figure 2 - Implementing an FSM in S
Page 17 and 18: Let’s consider these challenges i
Page 19 and 20: demonstrated by Dr. Howard Johnson,
Page 21 and 22: Pblocks can direct the flow of the
Page 23 and 24: Virtex-4 beats competing FPGAs in e
Page 25 and 26: In addition, you may also use techn
Page 27 and 28: Using Precision Sythesis, Block Mul
Page 29 and 30: 14-Bit, 125Msps ADC Only 395mW Lowe
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Page 33 and 34: QWERTY Building Blocks Our solution
Page 35 and 36: FPGA-Based Video Games Implementing
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Page 41: Smart Telematics Systems from Xilin
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Page 48 and 49: POWER MANAGEMENT Design Techniques
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Figure 1 - Period constraint in Syn
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DEBUGGING Using the actual constrai
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Bus Triggering and Display Traditio
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Designer Challenges for Pb-Free and
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A Shortcut to Effective Hierarchica
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Xilinx Education Services: Knowledg
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BIDIR_PAD(7.0) BIDIR this course, w
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Xilinx Virtex-4 FPGAs www.xilinx.co
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Xilinx CPLD www.xilinx.com/devices/
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Design Example: 1.5 volt LVCMOS 4mA
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Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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