Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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SYSTEM PERFORMANCE Achieve Breakthrough Performance in Your System Virtex-4 FPGAs set new records in system performance while consuming minimal power and providing superior signal integrity. by Adrian Cosoroaba Marketing Manager Xilinx, Inc. adrian.cosoroaba@xilinx.com Performance in today’s systems is defined by more than FPGA clock rates. Every system has different requirements, and the maximum achievable performance is determined by various factors such as logic fabric performance, I/O bandwidth, embedded processing, and DSP performance, among others. These requirements can also be subject to power restrictions, as well as signal integrity and cost budgets. Xilinx ® developed the Virtex-4 FPGA family after consulting hundreds of customers to address these requirements and make it easier than ever to meet system performance goals. In this article, we’ll look at how Virtex-4 FPGAs provide new and unique capabilities to help you meet diverse requirements for system performance. System Design Challenges With each new generation of devices, semiconductor vendors are able to offer higher clock rates, due to shrinking process geometries. However, today’s system performance challenges go beyond traditional glue logic and maximized clock rates. In a PC, for example, the real system performance bottleneck lies not in clock frequency but in how the other blocks of the system work together at the desired frequency. 16 Xcell Journal Third Quarter 2005
Let’s consider these challenges in the perspective of applications employing highperformance FPGAs. Seemingly diverse applications like video stream processing, packet data processing, storage systems, wireless base stations, and many others incorporate similar functions, including: • Incoming and outgoing data streams • Bridging multiple connectivity standards • Arithmetic and DSP (signal conditioning and data processing) • External memory interfacing • State machines • Data buffering • Embedded processing (Figure 1) To facilitate these applications, Virtex-4 FPGAs include common building blocks as embedded – yet parameterizable – hard IP. The integration of complex functions like DSP slices, embedded CPUs, dedicated I/O circuitry, and on-chip RAM (block RAM, FIFOs) provides you with unprecedented capabilities to build programmable systems within a single FPGA device. Meeting system requirements takes the right combination of I/O bandwidth, programmable logic, on-chip RAM, DSP, and embedded processing. To provide the ideal combination of functions, Virtex-4 FPGAs come in three flavors (LX, SX, and FX platforms) comprising 17 devices. Virtex-4 FPGAs offer not only enhanced logic fabric capabilities, but also customized XtremeDSP MACs and embedded PowerPC processors that give you enough performance headroom to reach your design performance goals. I/O bandwidth is often the limiting factor in the quest for performance. To remove I/O bottlenecks, Virtex-4 FPGAs have unique built-in 1 Gbps ChipSync sourcesynchronous circuitry and 622 Mbps to 10.3125 Gbps serial transceivers that can help you achieve bandwidth targets. System Performance Categories Let’s look at various aspects of performance and Virtex-4 FPGAs in the context of seven Incoming Data Stream FPGA CPU/APU D I/O Fabric S I/O Logic P Memory Interface Memory Buffer (DDR2, QDR II, etc.) major performance categories: logic fabric, embedded processing, DSP, on-chip RAM, high-speed serial, I/O memory bandwidth, and I/O LVDS bandwidth. Figure 2 offers a comparison with the nearest 90 nm FPGA vendor in each of these categories. Logic Fabric Performance Xilinx enhanced the performance of its already fast programmable logic fabric by building Virtex-4 devices with advanced 90 nm technology. A flexible look-up table (LUT) architecture (with the ability to covert any LUT into a 16-bit RAM or 16-bit shift register), a high-speed carry chain, and arithmetic blocks provide further performance gains. The 500 MHz global clocking structure, the key driver behind logic performance, is fully differential to reduce skew, jitter, and dutycycle distortion. Virtex-4 FPGAs also provide a hierarchical clocking structure (global and regional clocks) and clock management circuitry. Evaluations of logic fabric performance using a suite of realworld designs demonstrate a performance advantage as much as 70% above our nearest 90 nm competitor. Averaged across this suite of designs, the Virtex-4 performance advantage is 15%. This performance boost means that Virtex- 4 devices effectively provide an extra speedgrade advantage. Embedded Processing Virtex-4 FX platform FPGAs provide up to two enhanced PowerPC 405 cores, each delivering 702 DMIPS performance Third Quarter 2005 Xcell Journal 17 I/O Block RAM FIFO I/O Control Bus Figure 1 – FPGA-based system Outgoing Data Stream Figure 2 – Performance comparison for Virtex-4 FPGAs SYSTEM PERFORMANCE
Page 1 and 2: Xcell Issue 54 Third Quarter 2005 j
Page 3 and 4: EDITOR IN CHIEF Carlis Collins edit
Page 5 and 6: THIRD QUARTER 2005, ISSUE 54 Xcell
Page 7 and 8: Hardware Said ... The design flow s
Page 9 and 10: The second idea is to have the hard
Page 11 and 12: and automatic module generation wil
Page 13 and 14: Designing Control Circuits for High
Page 15: Figure 2 - Implementing an FSM in S
Page 19 and 20: demonstrated by Dr. Howard Johnson,
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Page 23 and 24: Virtex-4 beats competing FPGAs in e
Page 25 and 26: In addition, you may also use techn
Page 27 and 28: Using Precision Sythesis, Block Mul
Page 29 and 30: 14-Bit, 125Msps ADC Only 395mW Lowe
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Page 33 and 34: QWERTY Building Blocks Our solution
Page 35 and 36: FPGA-Based Video Games Implementing
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Page 41 and 42: Smart Telematics Systems from Xilin
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Tool Example Electrical Simulations
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Typically used bit patterns, or “
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ages and densities for increased fl
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see the start sequence, it continue
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The Virtex-4 ML450 Development Boar
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CONNECTIVITY Bridging System Packet
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put stream of SPI-4.2 data. A progr
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Controlling Noise A well-designed p
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Prototype Your PCIe ASIC HERE See u
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Figure 1 - Period constraint in Syn
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DEBUGGING Using the actual constrai
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Bus Triggering and Display Traditio
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Designer Challenges for Pb-Free and
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A Shortcut to Effective Hierarchica
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Xilinx Education Services: Knowledg
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BIDIR_PAD(7.0) BIDIR this course, w
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Xesium Global Clocking • 500MHz D
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Xilinx Virtex-4 FPGAs www.xilinx.co
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Xilinx CPLD www.xilinx.com/devices/
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Design Example: 1.5 volt LVCMOS 4mA
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Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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