Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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Xilinx delivers a broad range of Pb-Free and RoHS-compliant devices in the industry’s most advanced, high-performance packaging. In fact, Xilinx has already shipped over 5.8 million earth-friendly devices–more than any other supplier. With global programs for recycling, waste reduction, and energy management, we are proud to support our customers, and our environment. For more information visit www.xilinx.com/pbfree. www.xilinx.com/pbfree Pb-Free RoHS Compliant
Xilinx Virtex-4 FPGAs www.xilinx.com/devices/ Product Selection Matrix Virtex-4 FX (Embedded Processing & Serial Connectivity) Virtex-4 SX (Signal Processing) Virtex-4 LX (Logic) XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 64 x 24 64 x 36 96 x 52 128 x 52 160 x 68 192 x 84 64 x 40 96 x 40 128 x 48 64 x 24 96 x 28 128 x 36 128 x 52 160 x 56 192 x 64 192 x 88 192 x 116 CLB Array (Row x Column) 5,472 8,544 18,624 25,280 42,176 63,168 10,240 15,360 24,576 6,144 10,752 18,432 26,624 35,840 49,152 67,584 89,088 Slices CLB Resources 12,312 19,224 41,904 56,880 94,896 142,128 23,040 34,560 55,296 13,824 24,192 41,472 59,904 80,640 110,592 152,064 200,448 Logic Cells 10,944 17,088 37,248 50,560 84,352 126,336 20,480 30,720 49,152 12,288 21,504 36,864 53,248 71,680 98,304 135,168 178,176 CLB Flip Flops 87,552 136,704 297,984 404,480 674,816 1,010,688 163,840 245,760 393,216 98,304 172,032 294,912 425,984 573,440 786,432 1,081,344 1,425,408 Max. Distributed RAM Bits 36 68 144 232 376 552 648 1,224 2,592 4,176 6,768 9,936 128 192 320 2,304 3,456 5,760 48 72 96 160 200 240 288 336 Block RAM/FIFO w/ECC (18 kbits each) Memory Resources 864 1,296 1,728 2,880 3,600 4,320 5,184 6,048 Total Block RAM (kbits) 4 4 8 12 12 20 4 8 8 4 8 8 8 12 12 12 12 Digital Clock Managers (DCM) 0 0 4 8 8 8 0 4 4 0 4 4 4 8 8 8 8 Phase-matched Clock Dividers (PMCD) Clock Resources 320 320 448 576 768 896 320 448 640 320 448 640 640 768 960 960 960 Max Select I/O 9 9 11 13 15 17 9 11 13 9 11 13 13 15 17 17 17 Total I/O Banks Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Digitally Controlled Impedence I/O Resources 160 160 224 288 384 448 160 224 320 160 224 320 320 384 480 480 480 Max Differential I/O Pairs Third Quarter 2005 Xcell Journal 111 LDT-25, LVDS-25, LVDSEXT-25, BLVDS-25, ULVDS-25, LVPECL-25, LVCMOS25, LVCMOS18, LVCMOS15, PCI33, LVTTL, LVCMOS33, PCI-X, PCI66, GTL, GTL+, HSTL I (1.5V,1.8V), HSTL II (1.5V,1.8V), HSTL III (1.5V,1.8V), HSTL IV (1.5V,1.8V), SSTL2I, SSTL2II, SSTL18 I, SSTL18 II I/O Standards 32 32 48 128 160 192 128 192 512 32 48 64 64 80 96 96 96 XtremeDSP Slices DSP Resources 1 1 2 2 2 2 — — — — — — — — — — — PowerPC Processor Blocks 2 2 4 4 4 4 — — — — — — — — — — — 10/100/1000 Ethernet MAC Blocks Embedded Hard IP Resources 0 8 12 16 20 24 — — — — — — — — — — — RocketIO Serial Transceivers -10, -11, -12 -10, -11, -12 -10, -11, -12 -10, -11, -12 -10, -11, -12 -10, -11 -10, -11, -12 -10, -11, -12 -10, -11, -12 -10, -11, -12 -10, -11, -12 -10, -11, -12 -10, -11, -12 -10, -11, -12 -10, -11, -12 -10, -11, -12 -10, -11 Commercial (slowest to fastest) -10, -11 -10, -11 -10, -11 -10, -11 -10, -11 -10 -10, -11 -10, -11 -10, -11 -10, -11 -10, -11 -10, -11 -10, -11 -10, -11 -10, -11 -10, -11 -10 Industrial (slowest to fastest) Speed Grades 4,765,568 7,242,624 13,550,720 21,002,880 33,065,408 47,856,896 13,700,288 22,745,216 4,765,568 7,819,904 12,259,712 17,717,632 23,291,008 30,711,680 40,347,008 51,367,808 9,147,648 Configuration Memory Bits EasyPath Cost Reduction Solutions 4 — XCE4VLX25 XCE4VLX40 XCE4VLX60 XCE4VLX80 XCE4VLX100 XCE4VLX160 XCE4VLX200 XCE4VSX25 XCE4VSX35 XCE4VSX55 — XCE4VFX20 XCE4VFX40 XCE4VFX60 XCE4VFX100 XCE4VFX140 4VFX12 4VFX20 4VFX40 4VFX60 4VFX100 4VFX140 4VSX25 4VSX35 4VSX55 4VLX15 4VLX25 4VLX40 4VLX60 4VLX80 4VLX100 4VLX160 4VLX200 Package 1 Area MGT 2 Pins 240 240 240 SF363 17 x 17 mm — 240 320 320 448 320 448 448 448 FF668 27 x 27 mm — 448 640 640 640 768 768 768 FF1148 35 x 35 mm — 768 960 960 960 FF1513 40 x 40 mm — 960 320 (8) 3 352 (12) 3 352 (12) 3 FF672 27 x 27 mm 12 352 448 (12) 3 576 (16) 3 576 (20) 3 FF1152 35 x 35 mm 20 576 768 (20) 3 768 (24) 3 FF1517 40 x 40 mm 24 768 896 (24) 3 FF1760 42.5 x 42.5 mm 24 896 Pb-free solutions are available. For more information about Pb-free solutions, visit www.xilinx.com/pbfree. Important: Verify all data in this document with the device data sheets found at http://www.xilinx.com/partinfo/databook.htm Notes: 1. SFA Packages (SF): flip-chip fine-pitch BGA (0.80 mm ball spacing). FFA Packages (FF): flip-chip fine-pitch BGA (1.00 mm ball spacing). All Virtex-4 LX and Virtex-4 SX devices available in the same package are footprint-compatible. 2. MGT: RocketIO Multi-Gigabit Transceivers. 3. Number of available RocketIO Muti-Gigabit Transceivers. 4. EasyPath solutions provide conversion-free path for volume production.
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Xcell Issue 54 Third Quarter 2005 j
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EDITOR IN CHIEF Carlis Collins edit
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THIRD QUARTER 2005, ISSUE 54 Xcell
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Hardware Said ... The design flow s
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The second idea is to have the hard
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and automatic module generation wil
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Designing Control Circuits for High
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Figure 2 - Implementing an FSM in S
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Let’s consider these challenges i
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demonstrated by Dr. Howard Johnson,
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Pblocks can direct the flow of the
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Virtex-4 beats competing FPGAs in e
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In addition, you may also use techn
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Using Precision Sythesis, Block Mul
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14-Bit, 125Msps ADC Only 395mW Lowe
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Non-Symmetric Aspect Ratios/FWFT Ap
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QWERTY Building Blocks Our solution
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FPGA-Based Video Games Implementing
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The Atari 2600 Video Computer Syste
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The architecture wizards inside ISE
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Smart Telematics Systems from Xilin
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interfaces available, Microsoft int
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TXPLL TxData[7:0] FIFO an x4 link c
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POWER MANAGEMENT Design Techniques
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Power Estimation Tools Xilinx provi
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POWER MANAGEMENT Performance vs. Po
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POWER MANAGEMENT is the first time
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POWER MANAGEMENT Merging CPLD Featu
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POWER MANAGEMENT A Clear Choice Wit
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Page 67 and 68: Tool Example Electrical Simulations
Page 69 and 70: y Bill Hargin Product Manager, Hype
Page 71 and 72: Typically used bit patterns, or “
Page 73 and 74: ages and densities for increased fl
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Page 77 and 78: The Virtex-4 ML450 Development Boar
Page 79 and 80: CONNECTIVITY Bridging System Packet
Page 81 and 82: put stream of SPI-4.2 data. A progr
Page 83 and 84: Controlling Noise A well-designed p
Page 85 and 86: Prototype Your PCIe ASIC HERE See u
Page 87 and 88: knowing what is in R3 of the proces
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Page 95 and 96: Figure 1 - Period constraint in Syn
Page 97 and 98: DEBUGGING Using the actual constrai
Page 99 and 100: Bus Triggering and Display Traditio
Page 101 and 102: Designer Challenges for Pb-Free and
Page 103 and 104: A Shortcut to Effective Hierarchica
Page 105 and 106: Xilinx Education Services: Knowledg
Page 107 and 108: BIDIR_PAD(7.0) BIDIR this course, w
Page 109: Xesium Global Clocking • 500MHz D
Page 113 and 114: Xilinx CPLD www.xilinx.com/devices/
Page 116: Design Example: 1.5 volt LVCMOS 4mA
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Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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