Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

CONNECTIVITY
In this article, I’ll address the third reason
in detail. Although my focus is on
Xilinx ® Virtex-II Pro RocketIO technology,
the information would apply to
any serial interface, including RocketIO
transceivers in Virtex-4 devices.
Line Loss
An ideal lossless transmission line assumes
that a signal propagates down the line with
no energy loss. In other words, if a 1.0V
signal with a 1.0 ns rise time enters one end
of the line, the same 1.0V and 1.0 ns signal
will come out the far end.
Figure 1 – Reciever waveforms for a lossless line,
as well as 10, 20, and 40 in lines, showing
both attenuation and rise-time degradation
for a 2 GHz signal. (Simulated with Mentor
Graphics HyperLynx.)
This is a good approximation when signal
rise times are on the order of 1.0 ns (or
slower), and with trace lengths of 10 in (or
shorter). However, as rise times trend
toward 100 ps and lengths get significantly
longer (as in a backplane), the lossy effects
of transmission lines begin to influence signal
quality dramatically. As Figure 1 shows,
these effects – both attenuation and risetime
degradation – vary directly with
length at higher frequencies.
To describe and accurately predict the
behavior of real interconnects, two important
mechanisms that absorb energy from
the signal must be modeled:
• Resistive loss. From DC through frequencies
up to a few megahertz, the
current in a trace moves through the
entire cross-sectional area of the trace.
At higher frequencies, however, current
flows along the perimeter of a line
rather than uniformly across the entire
cross-section. As a result, the series
resistance of the signal and return path
conductors increases with the square
root of frequency as the effective crosssection
of the interconnect path is
reduced. Resistive loss is also referred
to as “skin effect.” But no matter what
you call it, it is the same phenomenon,
and something you should be concerned
about at high frequencies.
• Dielectric loss. The second important
loss mechanism is dielectric loss, which
is simply the conversion of electrical
energy from the alternating electric field
into heat. Dielectric loss, often specified
in decibels per meter, increases with frequency
and varies inversely with a material’s
“loss tangent” – a function of the
material’s resin type and molecular
structure. Depending on resin content,
“vanilla” FR-4 has a loss tangent ranging
from 0.02-0.03. Lower loss tangent
equates to more of the output signal
getting to its destination, as well as
higher material costs compared to FR-4.
GETEK, for example, has a loss tangent
of 0.012. Nelco 4000-13 is 0.01. And
the loss tangent for Rogers 4003 is as
low as 0.0027. For an actual design, you
will want to discuss the tradeoffs with
your board vendor.
Loss, Jitter, and ISI
I’ve often heard engineers use
the terms inter-symbol interference
(ISI), jitter, and loss
to refer to the same thing: the
unknown cause of a lessthan-optimal
signal or bitstream.
In fact, these are
different phenomena.
Random jitter is used to
describe random events that
result in a delay between the
expected and actual signal
transition. The distribution of
random effects follows a classic
Gaussian distribution, where
the results vary wider (in time)
as more data is observed. This
data is typically provided by
the driver manufacturer.
Deterministic jitter encompasses the
list of systematic interconnect effects that
will reoccur if you repeat the same stimulus.
Dielectric and resistive loss, as well as
crosstalk, reflections, via parasitics, returnpath
discontinuities, and any systematic
aspect of an interconnect design contribute
to deterministic jitter.
If the combined effects of random and
deterministic jitter are significant enough,
ISI will result, indicating that bit distinctions
have become “blurry” at the receiver.
This becomes particularly serious
when rise-time degradation becomes
comparable to the bit period of the signal.
As a result, the shape of the received
waveform will depend on the prior bit
pattern (ISI).
These effects are best modeled using
an oscilloscope that supports eye diagram
analysis. Eye diagrams provide a visual
display of the signal quality over many bit
transitions with both deterministic and
random jitter serving to close the “eye.”
At a glance, an eye diagram will show
if an interconnect is acceptable. Pass/fail
criteria are often specified by an eye mask,
shown as a blue hexagon on the left-hand
side of Figure 2. Eye masks, which conform
to the various SERDES specifications,
define minimum and maximum
keep-out regions where proper bit transitions
should not appear for proper receiver
interpretation of the driver’s intent.
Figure 2 – The eye shows encroachment on the XAUI eye mask
when using 10% pre-emphasis for a 36 in FR-4 transmission
path with four vias and two Teradyne VHDM-HSD5 connectors
(simulated with HyperLynx LineSim GHz).
70 Xcell Journal Third Quarter 2005