Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

Controlling Noise
A well-designed package is critical to signal
integrity. Noise can emanate from
many sources in a system. If the noise
source is on the board, there are some
potential solutions once you find out
where the problem is (probably after a
long and laborious debug process). If the
problem is in the package, you have little
or no choice but to change the design,
vendor, or parts. This is a time-consuming
process that can affect product
revenue significantly. For this
reason, it is imperative to have a welldesigned
low-inductance package.
When speeds were still fairly low,
short signal paths did not alter signal
characteristics. Today, with rise times
in the hundreds of picoseconds (even
if bit periods are a few nanoseconds),
the frequency components of signals
run into gigahertz, causing even very
short signal paths like package traces
to impact signals.
For every signal line, there is an associated
return path for the return currents.
For single-ended signals, these
return paths are usually GND or VCC
reference planes. To maintain a 50 ohm
line, the returns should be in close
proximity to the signal.
Although PCB traces are less of a
concern, you must pay close attention
to vias. For large FPGAs the breakout
region – the area between the package
balls to the PCB – is extremely critical,
as it comprises a dense concentration
of signal vias.
SSN is generally observed as
“ground bounce” and can be caused by
two different phenomena.
First, noise because of via-field
crosstalk is a function of loop inductance,
which is a function of the proximity of
ground/power reference pin locations to the
signal pin. Signal pins farther away from a
reference pin are more susceptible to noise.
This problem is exacerbated when a
number of I/Os in the region switch
simultaneously. Proper distribution of
ground/power and signal pins in a package
is extremely critical – in other words, a
good pinout architecture.
Second, maintaining a clean power supply
to the FPGA is also critical to maintain
acceptable signal integrity. Noise margins are
reduced as VCC values drop down to 1.2V.
Furthermore, any noise in the power rail
translates to jitter at the output, shrinking
available timing margins. As noise depends on
package inductance and the number of simultaneously
switching I/Os, optimal signaling
requires a good low-inductance package.
Ground Bounce / Voltage Collapse
+ System Jitter = Reduced Signal
Integrity and Smaller Valid Data “Eye”
Figure 1 – How noise and jitter can affect an eye diagram.
SparseChevron Pinout
Grounds Powers Signals
Figure 2 – Xilinx SparseChevron pinout places
return pins adjacent to each signal pin.
Tackling the SSN Challenge
One package that tackles the SSN challenge is
the Xilinx ® Virtex-4 FPGA package. Most
notably, the package enables better noise performance
on higher speed single-ended interfaces,
which are more susceptible to noise
than differential interfaces such as LVDS.
The pinout architecture of the package is
responsible for roughly 80% of the total
noise. The Virtex-4 FPGA package achieves
CONNECTIVITY
optimal pin distribution through a tiled
pattern – a regular array of signal, ground,
and power pins called SparseChevron
pinout (Figure 2).
The signal-to-ground-to-power ratio of
the package is 8:1:1. Because both power
and ground are equally effective as return
current paths, the package effectively has a
signal-to-return ratio of 4:1. Also, the pins
are distributed so that every signal pin is
adjacent to a return pin, ensuring
that the return current loop is
kept to a minimum.
Additionally, the abundance of
return paths in any given area of
the package provides a low
impedance path for the return
currents. The pinout also confines
noise from an aggressor to a
smaller area so that the influence
of the aggressor drops rapidly
with distance. Because crosstalk
noise is cumulative, this results in
a lower total SSN.
Simplifying Signal Termination
On-chip termination (active termination)
removes external components
and places termination
closest to where it matters (driver
or receiver).
To maintain the ideal 50 ohm
line impedance, it is normal
design practice to have termination
resistors on each signal. For
hundreds of signal I/Os, this can
translate to many hundreds of
external termination resistors. The
physical challenges of placing the
resistors on the board and their
connections to the power and
ground planes are not trivial.
The Xilinx Controlled
Impedance Technology (XCITE) on-chip
active I/O termination used in Virtex
FPGAs solves many of the problems associated
with signal termination. XCITE provides
both parallel and serial equivalent
options for single and differential termination.
Impedance is controlled using an
internal reference voltage and is available
on all I/O pins. This active termination
provides automatic temperature and volt-
Third Quarter 2005 Xcell Journal 83