Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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Product Selection Matrix Package Options and UserI/O 1 Spartan-3 (1.2V) Spartan-3E (1.2V) CLB Resources Memory Resources DSP CLK Resources I/O Features Speed PROM XC3S5000 XC3S4000 XC3S2000 XC3S1500 XC3S1000 XC3S400 XC3S200 XC3S50 XC3S1600E XC3S1200E XC3S500E XC3S250E XC3S100E I/O’s 124 173 264 391 487 565 712 784 Area2 Pins I/O’s 108 172 232 304 376 PQFP Packages (PQ) – wire-bond plastic QFP (0.5 mm lead spacing) 124 141 141 208 30.6 x 30.6 mm 158 158 VQFP Packages (VQ) – very thin QFP (0.5 mm lead spacing) 63 63 100 16.0 x 16.0 mm 66 66 TQFP Packages (TQ) – thin QFP (0.5 mm lead spacing) EasyPath Configuration Memory (Bits) Industrial Speed Grades (slowest to fastest) Commercial Speed Grades (slowest to fastest) I/O Standards Maximum I/O Number of Differential I/O Pairs Digitally Controlled Impedance # DCMs DCM Frequency (min/max) Dedicated Multipliers Block RAM (bits) # Block RAM Max. Distributed RAM Bits CLB Flip-Flops Equivalent Logic Cells Number of Slices CLB Array (Row x Col) System Gates (see note 1) 97 97 97 144 22.0 x 22.0 mm 108 108 Chip Scale Packages (CP) – wire-bond chip-scale BGA (0.5 mm ball spacing) 89 132 8 x 8 mm 92 92 FGA Packages (FT) – wire-bond fine-pitch thin BGA (1.0 mm ball spacing) 173 173 173 190 172 190 17 x 17 mm 256 FGA Packages (FG) – wire-bond fine-pitch BGA (1.0 mm ball spacing) 221 221 221 250 250 232 19 x 19 mm 320 304 304 21 x 21 mm 400 333 333 264 333 23 x 23 mm 456 Notes: 1. Numbers in table indicate maximum number of user I/Os. 2. Area dimensions for lead-frame products are inclusive of the leads. ✔ ✔ ✔ ✔ Spartan-3E Family – 1.2 Volt XC3S100E 100K 16 x 22 960 2,160 1920 15K 4 72K 4 5/326 2 NO 40 108 Single-ended -4 -5 -4 0.6M XC3S250E 250K 26 x 34 2448 5,508 4896 38K 12 216K 12 5/326 4 NO 68 172 LVTTL, LVCMOS3.3/2.5/1.8/ -4 -5 -4 1.4M 1.5/1.2, PCI 3.3V – 32/64-bit XC3S500E 500K 34 x 46 4656 10,476 9312 73K 20 360K 20 5/326 4 NO 92 232 33/66MHz, PCI-X 100MHz, -4 -5 -4 2.3M SSTL I 1.8/2.5, HSTL I 1.8, XC3S1200E 1200K 46 x 60 8672 19,512 17344 136K 28 504K 28 5/326 8 NO 124 304 HSTL III 1.8 -4 -5 -4 3.8M XC3S1600E 1600K 58 x 76 14752 33,192 29504 231K 36 648K 36 5/326 8 NO 156 376 Differential -4 -5 -4 5.9M LVDS2.5, Bus LVDS2.5, mini-LVDS, RSDS, LVPECL Spartan-3 and Spartan-3L Families – 1.2 Volt (see note 2) XC3S50 50K 16 x 12 768 1,728 1,536 12K 4 72K 4 24/280 2 YES 56 124 Single-ended -4 -5 -4 .4M LVTTL, LVCMOS3.3/2.5/1.8/ XC3S200 200K 24 x 20 1,920 4,320 3,840 30K 12 216K 12 24/280 4 YES 76 173 -4 -5 -4 1.0M 1.5/1.2, PCI 3.3V – 32/64-bit XC3S400 400K 32 x 28 3,584 8,064 7,168 56K 16 288K 16 24/280 4 YES 116 264 33MHz, SSTL2 Class I & II, -4 -5 -4 1.7M SSTL18 Class I, HSTL Class I, XC3S1000 XC3S1000L 1000K 48 x 40 7,680 17,280 15,360 120K 24 432K 24 24/280 4 YES 175 391 III, HSTL1.8 Class I, II & III, -4 -5 -4 3.2M GTL, GTL+ XC3S1500 XC3S1500L 1500K 64 x 52 13,312 29,952 26,624 208K 32 576K 32 24/280 4 YES 221 487 -4 -5 -4 5.2M XC3S2000 2000K 80 x 64 20,480 46,080 40,960 320K 40 720K 40 24/280 4 YES 270 565 Differential -4 -5 -4 7.7M LVDS2.5, Bus LVDS2.5, XC3S4000 XC3S4000L 4000K 96 x 72 27,648 62,208 55,296 432K 96 1,728K 96 24/280 4 YES 312 712 Ultra LVDS2.5, LVDS_ext2.5, -4 -5 -4 11.3M RSDS, LDT2.5, LVPECL XC3S5000 5000K 104 x 80 33,280 74,880 66,560 520K 104 1,872K 104 24/280 4 YES 344 784 -4 -5 -4 13.3M 376 23 x 23 mm 484 391 487 489 489 27 x 27 mm 676 565 633 633 31 x 31 mm 900 712 784 35 x 35 mm 1156 Xilinx Spartan-3 FPGAs www.xilinx.com/devices/ 112 Xcell Journal Third Quarter 2005 Pb-free solutions are available. For more information about Pb-free solutions visit www.xilinx.com/pbfree. Note: 1. System Gates include 20-30% of CLBs used as RAMs. 2. Spartan-3L devices offer reduced quiescent power consumption. Package offerings may vary slightly from those offered in the Spartan-3 family. See Package Selection Matrix for details. Important: Verify all data in this document with the device data sheets found at http://www.xilinx.com/partinfo/databook.htm For the latest information and product specifications on all Xilinx products, please visit the following links: Global Services www.xilinx.com/support/gsd/ Development Reference Boards www.xilinx.com/board_search/ Packaging www.xilinx.com/packaging/ FPGA and CPLD Devices www.xilinx.com/devices/ IP Reference www.xilinx.com/ipcenter/ Software www.xilinx.com/ise/ Configuration and Storage Systems www.xilinx.com/configsolns/
Xilinx CPLD www.xilinx.com/devices/ Product Selection Matrix – CoolRunner Series Package Options and User I/O I/O Features Speed Clocking CoolRunner XPLA3 CoolRunner-II XC2C512 XCR3512XL XCR3384XL XCR3256XL XCR3128XL XCR3064XL XCR3032XL XC2C512 XC2C384 XC2C256 XC2C128 XC2C64A XC2C32A Area 1 Pins QFN Packages (QFG) – quad flat no-lead (0.5 mm lead spacing) 32 5 x 5 mm 21 48 7 x 7 mm 37 PLCC Packages (PC) – wire-bond plastic chip carrier (1.27 mm lead spacing) 44 17.5 x 17.5 mm 33 33 36 36 Product Term Clocks per Function Block Global Clocks IQ Speed Grade Industrial Speed Grades (fastest to slowest) Commercial Speed Grades (fastest to slowest) Min. Pin-to-pin Logic Delay (ns) I/O Banking Maximum I/O Output Voltage Compatible Input Voltage Compatible Product Terms per Macrocell Macrocells System Gates CoolRunner-II Family – 1.8 Volt PQFP Packages (PQ) – wire-bond plastic QFP (0.5 mm lead spacing) 17 3 -6 -4 -6 -6 2 3.8 1.5/1.8/2.5/3.3 33 1.5/1.8/2.5/3.3 40 XC2C32A 750 32 173 173 173 164 172 180 30.6 x 30.6 mm 208 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 64 2 4.6 -5 -7 -7 -7 3 17 40 XC2C64A 1,500 64 VQFP Packages (VQ) – very thin QFP (0.5 mm lead spacing) 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 100 2 5.7 -6 -7 -7 -7 3 17 3.3 36 5 -5 -7 -10 -7 -10 -10 4 16 3.3 68 6 -6 -7 -10 -7 -10 -10 4 16 3.3 108 6 -6 -7 -10 -7 -10 -10 4 16 3.3 164 7.5 -7 -10 -12 -10 -12 -12 4 16 3.3 220 7.5 -7 -10 -12 -10 -12 -12 4 16 3.3 260 7.5 -7 -10 -12 -10 -12 -12 4 16 Third Quarter 2005 Xcell Journal 113 33 33 36 36 40 XC2C128 3,000 128 12.0 x 12.0 mm 44 68 84 64 80 80 16.0 x 16.0 mm 100 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 184 2 5.7 -6 -7 -7 -7 3 17 40 XC2C256 6,000 256 TQFP Packages (TQ) – thin QFP (0.5 mm lead spacing) 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 240 4 7.1 -7 -10 -10 -10 3 17 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 270 4 7.1 -7 -10 -10 -10 3 17 40 XC2C384 9,000 384 118* 108 120 100 118 118 22.0 x 22.0 mm 144 40 XC2C512 12,000 512 Chip Scale Packages (CP) – wire-bond chip-scale BGA (0.5 mm ball spacing) 56 6 x 6 mm 33 45 48 CoolRunner XPLA3 Family – 3.3 Volt 3.3/5 48 XCR3032XL 750 32 132 8 x 8 mm 100 106 Chip Scale Packages (CS) – wire-bond chip-scale BGA (0.8 mm ball spacing) 48 7 x 7 mm 36 40 3.3/5 48 XCR3064XL 1,500 64 3.3/5 48 XCR3128XL 3,000 128 108 12 x 12 mm 144 3.3/5 48 XCR3256XL 6,000 256 164 16 x 16 mm 280 3.3/5 48 XCR3384XL 9,000 384 FGA Packages (FT) – wire-bond fine-pitch thin BGA (1.0 mm ball spacing) 3.3/5 48 XCR3512XL 12,000 512 212 164 212 256 17 x 17 mm 184 212 212 FBGA Packages (FG) – wire-bond fine-line BGA (1.0 mm ball spacing) 260 220 324 23 x 23 mm 240 270 * JTAG pins and port enable are not pin compatible in this package for this member of the family. Note 1: Area dimensions for lead-frame products are inclusive of the leads.
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Xcell Issue 54 Third Quarter 2005 j
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EDITOR IN CHIEF Carlis Collins edit
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THIRD QUARTER 2005, ISSUE 54 Xcell
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Hardware Said ... The design flow s
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The second idea is to have the hard
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and automatic module generation wil
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Designing Control Circuits for High
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Figure 2 - Implementing an FSM in S
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Let’s consider these challenges i
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demonstrated by Dr. Howard Johnson,
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Pblocks can direct the flow of the
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Virtex-4 beats competing FPGAs in e
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In addition, you may also use techn
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Using Precision Sythesis, Block Mul
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14-Bit, 125Msps ADC Only 395mW Lowe
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Non-Symmetric Aspect Ratios/FWFT Ap
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QWERTY Building Blocks Our solution
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FPGA-Based Video Games Implementing
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The Atari 2600 Video Computer Syste
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The architecture wizards inside ISE
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Smart Telematics Systems from Xilin
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interfaces available, Microsoft int
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TXPLL TxData[7:0] FIFO an x4 link c
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POWER MANAGEMENT Design Techniques
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Power Estimation Tools Xilinx provi
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POWER MANAGEMENT Performance vs. Po
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POWER MANAGEMENT is the first time
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POWER MANAGEMENT Merging CPLD Featu
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POWER MANAGEMENT A Clear Choice Wit
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Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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