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Specification of Reactive Hardware/Software Systems - Electronic ...

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20 On <strong>Specification</strong> <strong>of</strong> <strong>Reactive</strong> <strong>Hardware</strong>/S<strong>of</strong>tware <strong>Systems</strong><br />

Other views are, as far as we have been able to check, not equipped with formal semantics.<br />

If a method does support a unified model (which has our preference), this should<br />

be expressed in a formal (executable) language. Separate views can then be expressed<br />

informally, though accompanying formal descriptions are in this case welcome too. An<br />

example <strong>of</strong> a method that starts with informal views and ends up with a formal unified<br />

model is ROOA [Mor94].<br />

The separate system views may be expressed in informal languages.<br />

The unified system model must be expressed in a formal<br />

language.<br />

S<strong>of</strong>tware Tools<br />

A major advantage <strong>of</strong> formal languages is that they have precisely defined syntax and<br />

semantics. This ensures that formal models are consistent, precise and unambiguous.<br />

Another major advantage <strong>of</strong> formal languages is that they allow the development <strong>of</strong><br />

advanced and indispensable s<strong>of</strong>tware tools that support the specification process. Important<br />

tools are<br />

(a) Model editors, syntactic analysers, semantic analysers and documentation generators.<br />

(b) Verification tools and dynamic analysers. For instance, equivalence checking or preorder<br />

checking can be applied to verify whether the system model exhibits the same<br />

observable behaviour as another system model (expressed in the same language)<br />

derived in a previous design phase. Model checking can be used to verify whether<br />

the system model satisfies behavioural properties expressed in a behavioural view<br />

or timing properties expressed in a timing view. In this case, the views must be<br />

expressed in a formal language too (for example in a temporal logic). Using a<br />

dynamic analyser certain predefined dynamic properties can be checked.<br />

(c) Simulation tools. These tools are used for verification and validation purposes, i.e.<br />

for the checking whether the system models satisfies the informal requirements.<br />

Simulation techniques can greatly increase the designer confidence in specifications<br />

[Fuc92].<br />

(d) Code generator tools. These tools automatically compile models into a target language<br />

(such as C or VHDL).<br />

(e) Transformation tools. These support the automatic transformation <strong>of</strong> models while<br />

keeping certain properties invariant. For instance, behaviour-preserving transformations<br />

change the structure <strong>of</strong> models, without modifying their observable<br />

behaviour. They are used to keep behaviour views and architectural views consistent<br />

or to integrate these views consistently into a formal unified model.<br />

All <strong>of</strong> these tools are more or less implemented in the LotoSphere integrated tool environment<br />

Lite [CS92]. In particular Lite supports equivalence checking and model<br />

checking, compilation into the programming language C, and behaviour-preserving<br />

transformations. SDL supports (a),(c) and (d) [Tur93]. SDL can be compiled to C, Pascal

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