3.22EjemploDRM007 Co..

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Introduction and Setup M68HC08 CPU INTERNAL BUS CPU REGISTERS CONTROL AND STATUS REGISTERS — 112 BYTES USER FLASH — 7680 BYTES USER RAM — 256 BYTES MONITOR ROM — 313 BYTES USER VECTOR SPACE — 46 BYTES OSC1 OSC2 CGMXFC RST IRQ ARITHMETIC/LOGIC UNIT (ALU) CLOCK GENERATOR MODULE SYSTEM INTEGRATION MODULE IRQ MODULE LOW-VOLTAGE INHIBIT MODULE COMPUTER OPERATING PROPERLY MODULE BREAK MODULE TIMER A AND TIMER B INTERFACE MODULES SERIAL COMMUNICATIONS INTERFACE MODULE POWER-ON RESET MODULE DDRA PORTA DDRB PORTB PULSE-WIDTH MODULATOR PTA6/ATD6 PTA5/ATD5 PTA4/ATD4 PTA3/ATD3 PTA2/ATD2 PTA1/ATD1 PTA0/ATD0 PTB6/TCH1B PTB5/TCH0B PTB4/TCH1A PTB3/TCH0A PTB2TCLKA PTB1/TxD PTB0/RxD PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PTC1/FAULT4 PTC1/FAULT4 V REFH ANALOG-TO-DIGITAL CONVERTER MODULE PULSE-WIDTH MODULATOR MODULE V DD V DDA V SSA V SS POWER Figure 1-1. MC68HC908MR8 Block Diagram DRM007 BLDC Motor <strong>Co</strong>ntrol Board for Industrial and Appliance Applications 18 Introduction and Setup MOTOROLA
Introduction and Setup MC68HC908MR8 Features of the MC68HC908MR8 include: • High-performance M68HC08 architecture • Fully upward-compatible object code with M6805, M146805, and M68HC05 Families • 8-MHz internal bus frequency • 8 Kbytes of on-chip FLASH • On-chip programming firmware for use with host PC • On-chip random-access memory (RAM) 256 bytes • 12-bit, 6-channel center-aligned or edge-aligned PWMMC • Serial communications interface module (SCI) • Two 16-bit, 2-channel timer interface modules (TIMA and TIMB) • Eight high current sink and source pins (PTA1/ATD1, PTA0/ATD0, PTB6/TCH1B, PTB5/TCH0B, PTB4/TCH1A, PTB3/TCH0A, PTB2/TCLKA, and PTB1/TxD) • Clock generator module (CGM) • Digitally filtered low-voltage inhibit (LVI), software selectable for ±5 percent or ±10 percent tolerance • 10-bit, 4- to7-channel analog-to-digital converter (ADC) • System protection features: – Optional computer operating properly (COP) reset – Low-voltage detection with optional reset – Illegal opcode detection with optional reset – Illegal address detection with optional reset • Fault detection with optional PWM disabling • Available packages: – 32-pin low-profile quad flat pack (LQFP) – 28-pin dual in-line package (PDIP) – 28-pin small outline package (SOIC) BLDC Motor <strong>Co</strong>ntrol Board for Industrial and Appliance Applications DRM007 MOTOROLA Introduction and Setup 19
Page 1: BLDC Motor Control Board for Indust
Page 4 and 5: Revision History To provide the mos
Page 6 and 7: List of Sections DRM007 BLDC Motor
Page 8 and 9: Table of Contents Section 2. Operat
Page 10 and 11: Table of Contents 5.9.9 Signed Word
Page 12 and 13: List of Figures Figure Title Page 5
Page 14 and 15: List of Tables DRM007 BLDC Motor Co
Page 16 and 17: Introduction and Setup 1.2 Introduc
Page 20 and 21: Introduction and Setup • Low-powe
Page 22 and 23: Introduction and Setup OR PRESCALER
Page 24 and 25: Introduction and Setup 1.4.3 PWM Co
Page 26 and 27: Introduction and Setup Brushless dc
Page 28 and 29: Introduction and Setup V BUS PWM1 P
Page 30 and 31: Introduction and Setup 1.6.6 Target
Page 32 and 33: Introduction and Setup The Hall sen
Page 34 and 35: Introduction and Setup To program t
Page 36 and 37: Introduction and Setup HALL EFFECT
Page 38 and 39: Operational Description 2.3 Electri
Page 40 and 41: Operational Description By pressing
Page 42 and 43: Operational Description 2.5.5 J5
Page 44 and 45: 44 Schematics and Bill of Materials
Page 50 and 51: Schematics and Bill of Materials 6
Page 52 and 53: Schematics and Bill of Materials 4
Page 54 and 55: Schematics and Bill of Materials DR
Page 56 and 57: Hardware Design Considerations 4.2
Page 62 and 63: Hardware Design Considerations VCC
Page 64 and 65: Hardware Design Considerations As a
Page 66 and 67: Hardware Design Considerations This
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Hardware Design Considerations 4.12
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Hardware Design Considerations DRM0
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Software Design Considerations 5.9.
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Software Design Considerations Clos
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Software Design Considerations The
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Software Design Considerations TIMA
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Software Design Considerations 5.5
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Software Design Considerations the
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Software Design Considerations 5.8
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Software Design Considerations inte
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Software Design Considerations DRM0
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Practical Results Figure 6-2 shows
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Practical Results Taking the rectif
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Practical Results DRM007 BLDC Motor
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Source Code 7.2 Include Files 7.2.1
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Source Code #define SCS1 (*(volatil
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Source Code 7.2.2 START08.H ; /****
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Source Code #pragma DATA_SEG DEFAUL
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Source Code // Function Headers voi
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Source Code void CtrlLCD(UBYTE cont
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Source Code 7.3 Source Code Files 7
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Source Code ZeroOut: ; LDA _startup
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Source Code Loop1: finished: } } DB
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Source Code 7.3.2 MAIN.C ; /*******
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Source Code EnableInterrupts(); do
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Source Code } else { if((PORTB & OP
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Source Code #include "MR8IO.h" #inc
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Source Code #endif /* Initialize ti
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Source Code LDX #0x12 DIV LDHX #0x0
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Source Code */ SINT16 PIController
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Source Code /**********************
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Source Code { #ifdef MOS_3_COM PVAL
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Source Code #ifdef MOS_2_COM PVAL1
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Source Code PVAL3 = _newPWM; PVAL4
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Source Code TurnOffAllPWMOutputs();
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Source Code /**********************
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Source Code void MovCursorLCD(UBYTE
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Source Code /**********************
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