Top-down digital design flow - Microelectronic Systems Laboratory

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Top-down digital design flowiiDocument historyVersion Date Notes1.0 2003 Initial version.2.0.1 23 apr 04 Updated for new EDA tool releases.First design example (adder-subtractor) only.2.0.2 26 may 04 Minor changes.2.0.3 3 jun 04 Minor changes.3.0.1 11 oct 05 Use Cadence Encounter as P&R tool.3.0.2 6 dec 05 Minor issues fixed.3.1 Nov 2006 PaR chapter with SoC Encounter rewritten.AVx / version 3.1 - November 2006
Top-down digital design flow / Table of ContentsiiiTable of ContentsChapter 1: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Top-down design flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Design project organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 EDA tools and design kit configuration . . . . . . . . . . . . . . . . . . . . . . . . 41.4 Installation of the AMS design kit . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.5 VHDL example: Adder-subtractor . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.6 Text editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.7 Design flow steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Chapter 2: VHDL and Verilog simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1 Starting the Modelsim graphical environment . . . . . . . . . . . . . . . . . . . 92.2 Simulation of (pre-synthesis) RTL VHDL models . . . . . . . . . . . . . . . . . .102.3 Simulation of the post-synthesis VHDL model with timing data . . . . . . . .122.4 Simulation of the post-route Verilog model with timing data . . . . . . . . .14Chapter 3: Logic synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.1 Starting the Design Vision graphical environment . . . . . . . . . . . . . . . . .173.2 RTL VHDL model analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183.3 Design elaboration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183.4 Design environment definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193.5 Design constraint definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203.6 Design mapping and optimization . . . . . . . . . . . . . . . . . . . . . . . . . . .213.7 Report generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233.8 VHDL/Verilog gate-level netlist generation and post-synthesis timing data(SDF) extraction 263.9 Design constraints generation for placement and routing . . . . . . . . . . .273.10 Design optimization with tighter constraints . . . . . . . . . . . . . . . . . . . .283.11 Using scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Chapter 4: Standard cell placement and routing . . . . . . . . . . . . . . . . . . . . . 334.1 Starting the Encounter graphical environment . . . . . . . . . . . . . . . . . .334.2 Design import . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354.3 Floorplan Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374.4 Power ring/stripe creation and routing . . . . . . . . . . . . . . . . . . . . . . .384.5 Global net connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404.6 CAP cell placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404.7 Operating conditions definition . . . . . . . . . . . . . . . . . . . . . . . . . . . .414.8 Core cell placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424.9 Post-placement timing analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . .434.10 Clock tree synthesis (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .444.11 Design routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .474.12 Post-routing timing optimization and analysis . . . . . . . . . . . . . . . . . . .484.13 Filler cell placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .484.14 Design checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .494.15 Report generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .504.16 Post-route timing data extraction . . . . . . . . . . . . . . . . . . . . . . . . . . .514.17 Post-route netlist generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .514.18 GDS2 file generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .514.19 Design import in Virtuoso . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524.20 Using scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53AVx / version 3.1 - November 2006
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