Top-down digital design flow - Microelectronic Systems Laboratory

Top-down digital design flow / Chapter 4: Standard cell placement and routing 494.14 Design checksThe Verify menu has a number of items to check that the design has been properly placed and routed.Select Verify -> Verify Connectivity... in the main menu. Definethe report file as PAR/RPT/addsub_nbits8-conn.rpt.Click OK. The console displays the results:******** Start: VERIFY CONNECTIVITY ********Start Time: Thu Dec 1 18:52:00 2005Design Name: addsub_NBITS8Database Units: 1000Design Boundary: (0.0000, 0.0000) (153.0500,136.9000)Error Limit = 1000; Warning Limit = 50Check all netsBegin SummaryFound no problems or warnings.End SummaryEnd Time: Thu Dec 1 18:52:00 2005******** End: VERIFY CONNECTIVITY ********Verification Complete : 0 Viols. 0 Wrngs.Select Verify -> Verify Geometry... in the main menu. In theAdvanced tab, define the report file asPAR/RPT/addsub_nbits8-geom.rpt.Click OK.The console displays the results:*** Starting Verify Geometry (MEM: 222.2)VERIFY GEOMETRY ...... Starting VerificationVERIFY GEOMETRY ...... InitializingVERIFY GEOMETRY ...... Deleting ExistingViolationsVERIFY GEOMETRY ...... Creating Sub-AreasVERIFY GEOMETRY ...... SubArea : 1 of 1VERIFY GEOMETRY ...... Cells : 0 Viols.VERIFY GEOMETRY ...... SameNet : 0 Viols.VERIFY GEOMETRY ...... Wiring : 0 Viols.VERIFY GEOMETRY ...... Antenna : 0 Viols.VERIFY GEOMETRY ...... Sub-Area: 1 complete 0 Viols. 0 Wrngs.Begin Summary ...Cells : 0SameNet : 0Wiring : 0Antenna : 0Short : 0Overlap : 0End SummaryVerification Complete : 0 Viols. 0 Wrngs.AVx / version 3.1 - November 2006