Top-down digital design flow - Microelectronic Systems Laboratory
Top-down digital design flow - Microelectronic Systems Laboratory
Top-down digital design flow - Microelectronic Systems Laboratory
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<strong>Top</strong>-<strong>down</strong> <strong>digital</strong> <strong>design</strong> <strong>flow</strong> / Chapter 2: VHDL and Verilog simulation 16Then click OK in the remaining Start Simulation dialog box to load the mapped netlist. Clock to outputdelays of the order of 800ps to 1000ps should be visible in the wave window.More accurate values for the delays can be obtained using a smaller time unit in simulation (e.g., 10ps orless).AVx / version 3.1 - November 2006
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