Top-down digital design flow - Microelectronic Systems Laboratory

Top-down digital design flow / Chapter 3: Logic synthesis 183.2 RTL VHDL model analysisThe analysis phase compiles the VHDL model and checks that the VHDL code is synthesizable.Select File -> Analyze... in the main menu.Use the Add... button to add all the VHDL sources youneed to analyze.In the case you have more than one VHDL file to analyze,be careful to list the files in the correct analysis order.Another way is to select all the files and click onthe button Automatic Ordering to let the tool find theright dependency order. This button is only activewhen several VHDL files are listed.Click OK.3.3 Design elaborationThe elaboration phase performs a genericpre‐synthesis of the analyzed model. It essentiallyidentifies the registers that will beinferred.Select File -> Elaborate... in the main menu.The DEFAULT library is identical to theWORK library. Specify the value for theNBITS generic parameter to 8.Click OK.The console now displays the inferred registers and the kind of reset (here asynchronous reset ‐ AR: Y).Note the name addsub_NBITS8 given to the elaborated entity.AVx / version 3.1 - November 2006