Top-down digital design flow - Microelectronic Systems Laboratory

Top-down digital design flow / Chapter 4: Standard cell placement and routing 354.2 Design importImporting the design into Encounter involves specifying the following setup information:• Design libraries and files. This includesinformation on the technologicalprocess and the cell library inthe LEF (Layout Exchange Format)format. LEF files provides informationsuch as metal and via layersand via generate rules which isused for routing tasks. They alsoprovide the minimum informationon cell layouts for placement androuting.• Gate‐level netlist. This relates tothe (Verilog) netlist to be placed androuted.•Timing libraries. This includes informationon the cell timings (delays,setup/hold times, etc.).•Power information. This relates tothe power nets to use in the layout.To start the design import, selectDesign -> Design Import... in themain menu. Then, click on the Load...button and load the filePAR/CONF/c35b4_std.confThis file defines a basic import configuration.There is a number of additions and changes to bring to the initial configuration. The new configurationwill then be saved for future uses.The first information to add is the netlist. Click on the ... button on the right of the Verilog Files field. Youget a new dialog window with only one pane. Click on the top‐right icon to get the full window.Remove the VERILOG/none line in the left pane.Select the Verilog netlist file HDL/GATE/addsub_dfl_nbits8_mapped.v (or the Verilog netlist you want toplace and route), add it to the left pane and close the window. It is assumed here that the imported netlistis the one generated for the 10 ns clock period.AVx / version 3.1 - November 2006