Top-down digital design flow - Microelectronic Systems Laboratory

Top-down digital design flow / Chapter 4: Standard cell placement and routing 36In the Design Import window, select the Auto Assign box to let the tool extract the top cell name from thefile. If the Verilog file includes more than one design (more than one top module name), you need to givethe name of the top module to use explicitly.In the “LEF files” and “Common Timing Libraries” fields, you should remove the reference to the IO padlibrary if you don’t intend to include pads, namely:/softs/dkits/ams/v3.70/artist/HK_C35/LEF/c35b4/IOLIB_4M.lef/softs/dkits/ams/v3.70/liberty/c35_3.3V/c35_IOLIB_4M.libIn the Power tag, you can keep onlythe vdd! and gnd! power nets if youwon’t add periphery cells. Thenames of power and ground netsmust be the same as the ones used inthe LEF file that describes the standardcells.In the Timing tag, you can specify the timingconstraints that you used for synthesis.Select the file that has been generated duringlogic synthesis (3.6 Design mapping and optimization):SYN/SDC/addsub_dfl_nbits8_mapped.sdcOnly timing information in the constraintfile is actually used by Encounter.The rest of the settings can be left as is. You can now save the updated configuration in the filePAR/CONF/addsub_nbits8.conf by clicking on the Save... button.Finally, click on OK. The configuration is then read in.To reload a configuration, select Design -> Design Import... in the main menu. Then, click on the Load...button and load the configuration file from the PAR/CONF directory.AVx / version 3.1 - November 2006