Top-down digital design flow - Microelectronic Systems Laboratory

Top-down digital design flow / Chapter 4: Standard cell placement and routing 46To get a report on the clock tree synthesis, select Clock -> Report Clock Tree... in the main menu.Specify the file PAR/RPT/addsub_nbits8.ctsrpt as the reportfile.Click OK.The following report is also displayed in the Encounterconsole:reportClockTree Option :-report PAR/RPT/addsub_nbits8.ctsrpt**** Clock Tree clk Stat ****Total Clock Level : 1***** Top Nodes *****clk delay[0(ps) 0(ps)] ( a_reg_reg_7_/C a_reg_reg_6_/C a_reg_reg_5_/Ca_reg_reg_4_/C a_reg_reg_3_/C a_reg_reg_2_/C a_reg_reg_1_/C a_reg_reg_0_/C b_reg_reg_7_/C b_reg_reg_6_/C b_reg_reg_5_/C b_reg_reg_4_/Cb_reg_reg_3_/C b_reg_reg_2_/C b_reg_reg_1_/C b_reg_reg_0_/C z_reg_0_/Cz_reg_1_/C z_reg_2_/C z_reg_3_/C z_reg_4_/C z_reg_5_/C z_reg_6_/Cz_reg_7_/C )Level 1 (Total=24 Sink=24)Total Sinks : 24********** Clock clk Pre-Route Timing Analysis **********Nr. of Subtrees : 1Nr. of Sinks : 24Nr. of Buffer : 0Nr. of Level (including gates) : 0Max trig. edge delay at sink(R): a_reg_reg_7_/C 9.6(ps)Min trig. edge delay at sink(R): a_reg_reg_4_/C 0.7(ps)(Actual)(Required)Rise Phase Delay : 0.7~9.6(ps) 0~10000(ps)Fall Phase Delay : 0.7~9.6(ps) 0~10000(ps)Trig. Edge Skew : 8.9(ps) 300(ps)Rise Skew: 8.9(ps)Fall Skew: 8.9(ps)Max. Rise Buffer Tran. : 0(ps) 400(ps)Max. Fall Buffer Tran. : 0(ps) 400(ps)Max. Rise Sink Tran. : 15.5(ps) 400(ps)Max. Fall Sink Tran. : 15.5(ps) 400(ps)Min. Rise Buffer Tran. : 0(ps) 0(ps)Min. Fall Buffer Tran. : 0(ps) 0(ps)Min. Rise Sink Tran. : 6.5(ps) 0(ps)Min. Fall Sink Tran. : 6.5(ps) 0(ps)Several clock report files are also available in the PAR/CTS directory.It is recommended to save the new stage of the design. Select Design -> Save Design... in the main menuand save the current state in the file PAR/DB/addsub_nbits8-cts.enc.AVx / version 3.1 - November 2006