Top-down digital design flow - Microelectronic Systems Laboratory

Top-down digital design flow / Chapter 4: Standard cell placement and routing 374.3 Floorplan SpecificationThe floorplan defines the actual form, or aspect ratio, the layout will take, the global and detailed routinggrids, the rows to host the core cells and the I/O pad cells (if required), and the location of the corner cells(if required).Select Floorplan -> Specify Floorplan... in themain menu.Define an aspect ratio of 1.The default core utilization is 85%, whichmeans that 15% of the core area will be free forpossible future buffer insertions or cell replacements.The other utilization ratio (Std. Utilization)refers to the density of the standard cells.The space between the I/Os and the core shouldbe large enough to host a number of power andground rings and possible periphery cells (I/Opads). Define I/O to core distances of 16 microns.This is enough as there will be one powerand one ground ring of 4 micron width eachand there won’t be any pads in the layout.The cell rows will be abbutted and flipped eachtwo row to share VDD and ground power rails.Clicking on Apply updates the numbers to actualvalues.Click OK. The display design area pane now shows the defined floorplan with the required number ofrows.It is a good idea to save the design at that stage to allowrestarting here quickly without needing to redo all theprevious steps.Select Design -> Save Design... in the main menu andsave the current state in the filePAR/DB/addsub_nbits8-fplan.enc.The data are actually saved in the directoryPAR/DB/addsub_nbits8-fplan.enc.dat.To restore design data, selectDesign -> Restore Design... in the main menu and selectthe .enc file to read in the PAR/DB directory.AVx / version 3.1 - November 2006