Top-down digital design flow - Microelectronic Systems Laboratory

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Top-down digital design flow / Table of ContentsivAVx / version 3.1 - November 2006
Top-down digital design flow 1Chapter 1: IntroductionThis document details the typical steps of a top‐down digital VHDL/Verilog design flow with the help ofone simple design example.The following tools are considered in this document:• Modelsim v6.1b or higher, from Mentor Graphics.• Design Compiler and Design Vision 2005.09 or higher from Synopsys.• Encounter 4.1 and IC 5.0.33 or higher from Cadence Design Systems.The design kit used is the Hit‐Kit 3.70 from AMS. The process is the 0.35 micron 4‐metal CMOS calledC35B4.Each of the next chapters in this document is addressing a specific set of tasks. Chapter 2 is about VHDLand Verilog simulation, chapter 3 is about logic synthesis and chapter 4 is about place and route. Steps inthese chapters are not necessarily to be done in the given sequence. Go to “1.7 Design flow steps” to get atypical sequence of steps supporting a top‐down approach.1.1 Top-down design flowFigure 1.1: Top-down design flow.AVx / version 3.1 - November 2006
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