Top-down digital design flow - Microelectronic Systems Laboratory

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Top-down digital design flow / Chapter 3: Logic synthesis 32AVx / version 3.1 - November 2006
Top-down digital design flow 33Chapter 4: Standard cell placement and routingThis chapter presents the main steps to perform the placement and the routing of the synthesized gate‐levelnetlist using standard cells from the AMS design kit. The tool used here is Cadence Encounter. The cdsdocon‐line command gives access to the Cadence documentation. The tool also has a Help menu.4.1 Starting the Encounter graphical environmentTo start the Encounter environment, enter the encounter command in a new Unix shell:[85]vachoux@lsmsun1-ADDSUB> encounter -log PAR/LOG/encounter -overwriteMain menuToolbar widgetsStatusTool widgetsdisplay design areaDesign display areaSelectabilitytogglesVisibilitytogglesDesign viewsSatellite windowColoroptionsName of selected or queried objectEncounter consoleAuto query ofobjects when enabledNumberof selected objectsAVx / version 3.1 - November 2006
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Top-down digital design flow - Microelectronic Systems Laboratory

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