Top-down digital design flow - Microelectronic Systems Laboratory

Top-down digital design flow / Chapter 4: Standard cell placement and routing 434.9 Post-placement timing analysisThe timing analysis engine in Encounter can now be run toget a relatively good idea of the timing performances of thedesign. It actually performs a trial routing and a parasiticextraction based on the current cell placement.Select Timing -> Timing Analysis... in the main menu. Definethe path for the slack report file. Click OK.In the Encounter console window you get a summary of thetiming analysis:*** Dump slack report (0:00:00.0)**Info: no slack violation path.Slack File : PAR/RPT/addsub_nbits8.slktargetSlack : 0.000 ns-------------------- ------- -------Slack Range (ns) Count Sum-------------------- ------- -------( 2.299 ~ 2.000] 1 1( 2.000 ~ 2.500] 0 1-------------------- ------- -------Total negative slacks(TNS)=0Worst negative slacks(WNS)=2.299The design is not critical as the slackis positive (2.299 ns). Comparingwith the timing report obtained duringlogic synthesis (3.7 Report generation),we notice that the slackhere is slightly higher. The differencecome from a more accuratecomputation of parasitics delays.To get more details on the criticalpath, selectTiming -> Timing Debug-> Slack Browser... in the mainmenu. Load the slack report file generatedpreviously.Check the Show Path Schematic boxto see the path schematic. Doubleclickon the first path in the upperlist.The critical path is the same as in theone found during logic synthesis.AVx / version 3.1 - November 2006