Top-down digital design flow - Microelectronic Systems Laboratory

Top-down digital design flow / Chapter 4: Standard cell placement and routing 404.5 Global net connectionsThis step assigns pins or nets to global power and ground nets. The imported Verilog netlist does not mentionany power and ground connections. However, the cells that will be placed do have power/ground pinsthat will need to be routed to the global power/ground nets defined for the block.Select Floorplan -> Global Net Connections... in the main menu.The left pane (Connection List) is initially empty. For each VDD and ground net:• Check the Pins field and enter the pin name (vdd! or gnd!).• Fill the To Global Net field with either vdd! or gnd!.• Click on Add to List. The left pane now includes the related global net connection.Click on Apply and then on Close.The Encounter console then reports on the number of power pin to global net connections that have beenmade (the actual number may vary depending on the number of rows defined in the floorplan):44 new pwr-pin connections were made to global net 'vdd!'.44 new gnd-pin connections were made to global net 'gnd!'.4.6 CAP cell placementThe AMS design kit requires that physical‐only terminationcells must be placed at each row ends. The so‐called CAPcells are used to properly bias the P+ and N+ substrates.To do this, select Place -> Filler -> Add End Cap... in themain menu. Then, select the ENDACPL cell as the cell to placeat the beginning of each row and the ENDCAPR cell as the cellto place at the end of each row.Click OK. The added cells are now visible in the Physicalview (you might need to redraw the display).AVx / version 3.1 - November 2006