Top-down digital design flow - Microelectronic Systems Laboratory

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Top-down digital design flow / Chapter 4: Standard cell placement and routing 384.4 Power ring/stripe creation and routingThis step generates the VDD and ground power rings around the core and optionally adds a number ofvertical and/or horizontal power stripes across the core. Stripes ensure a proper power distribution in largecores. They are not strictly required here as the design is small.Select Floorplan -> Power Planning -> Add Rings... in the main menu.The Net(s) field defines the number and the kinds of rings from the core. In our case, there will be first aground ring around the core and a VDD ring around the ground ring. The net names should be consistentwith the power net names in the cell LEF file.The ring configuration defines ring widths of 4 micron spaced by 0.6 micron.The rings will be placed in the center of the channel between thecore and the chip boundary (or the IO pads, if any). Check the Center inchannel box in the Ring Configuration part.It is possible to extend the ring segments to reach the core boundary.Click on the Advanced tab and click on the segments you’d like to extend.Other power and ground side trunks can be defined by selectingonly horizontal or vertical segments.Click OK to generate the rings.AVx / version 3.1 - November 2006
Top-down digital design flow / Chapter 4: Standard cell placement and routing 39To add power stripes, select Floorplan -> Power Planning -> Add Stripes... in the main menu.The Net(s) field defines the pattern. Here a singlepattern will be generated (select Number ofsets and insert 1). Each stripe will be 2 micronwide and the space between them will be 1 micron.Check Relative from core or selected area andenter the value 60 (micron) in the X from leftfield. The two stripes will be vertically placednear the center of the core.It is possible to measure sizes by using the ruler(or hit the k binding key). Hit K to remove thelast ruler or press ESC to remove all rulers.Click OK to generate the stripes.It is possible to remove the stripes by selectingthem and hitting the Delete key.Additionally, the commandFloorplan -> Clear Floorplan...allows you to delete all or parts of the floorplanobjects.Now, it is possible to route the power grid. Select Route -> SRoute... in the main menu. All default valuesare fine. Click OK to do the routing. The design now looks like below:It is recommended to save the new stage of the design. Select Design -> Save Design... in the main menuand save the current state in the file PAR/DB/addsub_nbits8-pring.enc.AVx / version 3.1 - November 2006
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Top-down digital design flow - Microelectronic Systems Laboratory

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