Top-down digital design flow - Microelectronic Systems Laboratory
Top-down digital design flow - Microelectronic Systems Laboratory
Top-down digital design flow - Microelectronic Systems Laboratory
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<strong>Top</strong>-<strong>down</strong> <strong>digital</strong> <strong>design</strong> <strong>flow</strong> / Chapter 4: Standard cell placement and routing 484.12 Post-routing timing optimization and analysisA final timing optimization may bedone on the routed <strong>design</strong>. SelectTiming -> Optimization... in the mainmenu.Select the postRoute box.Click OK.The results of the optimization is displayedin the Encounter console:Setup modeWorst Slack: 2.341nsTNS: 0.000ns ViolatingPaths: 0Pathgroup Slacksreg2reg: 2.341nsin2reg: 2.681nsreg2out: 8.959nsin2out: 0.000nsDensity: 96.053%Real DRV (fanout, cap, tran): (0, 0, 0)Total DRV (fanout, cap, tran): (0, 0, 0)The worst slack has been improved a bit to 2.341 ns.4.13 Filler cell placementFiller cells will fill remaining holes in the rows and ensure the continuity of power/ground rails and N+/P+wells in the rows.To fill the holes with filler cells, selectPlace -> Filler -> Add Filler... in the main menu.Select the cells FILLRT1, FILLRT2, FILLRT5, FILLRT10,FILLRT25 FILL1, FILL2, FILL5, FILL10, and FILL25 and click OKto place the filler cells.AVx / version 3.1 - November 2006
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