Top-down digital design flow - Microelectronic Systems Laboratory

Top-down digital design flow / Chapter 3: Logic synthesis 26A new window and the console now display the report:**********************************Report : resourcesDesign : addsub_NBITS8Version: X-2005.09-SP4Date : Thu Nov 30 11:20:15 2006**********************************Resource Sharing Report for design addsub_NBITS8 in file/home/vachoux/educ/edabd/ADDSUB_06/HDL/RTL/addsub_dfl.vhd============================================================================| | | | Contained | || Resource | Module | Parameters | Resources | Contained Operations |============================================================================| r248 | DW01_addsub | width=8 | | add_30 sub_30 |============================================================================Implementation Report============================================================================| | | Current | Set || Cell | Module | Implementation | Implementation |============================================================================| r248 | DW01_addsub | rpl | |============================================================================No multiplexors to reportYou can see that the inferred arithmetic component is implemented as a ripple‐carry (rpl) architecture. Thetool uses the so‐called DesignWare library which contains a number of predefined HDL models of blocks(arithmetic, etc.) with several possible architectures for each block. The best architecture is selected to meetthe design constraints.3.8 VHDL/Verilog gate-level netlist generation and post-synthesis timingdata (SDF) extractionThis step generates a VHDL model of the mapped design for simulation and a Verilog model of the samedesign to be used as input to the placement and routing tool. It also generates a SDF (Standard Delay Format)file that includes the gate delays. Care should be taken to use the right naming scheme when generatingthe SDF file, otherwise the back‐annotation of the delays onto the VHDL or Verilog netlists forsimulation will fail. Here we only consider the back‐annotation of VHDL netlists.Before generating the VHDL netlist, it is required to apply some VHDL naming rules to the design. This isdone by entering the following command in the console (be sure that the entity addsub_NBITS8 is selectedin the hierarchy window):change_names -hierarchy -rules vhdl -verboseSave the mapped design in the fileaddsub_dfl_nbits8_mapped.vhdl in the directoryHDL/GATE.Note: the dialog window creates VHDLfiles with the .vhdl extension rather than.vhd as used so far.AVx / version 3.1 - November 2006