Top-down digital design flow - Microelectronic Systems Laboratory
Top-down digital design flow - Microelectronic Systems Laboratory
Top-down digital design flow - Microelectronic Systems Laboratory
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<strong>Top</strong>-<strong>down</strong> <strong>digital</strong> <strong>design</strong> <strong>flow</strong> 17Chapter 3: Logic synthesisThis chapter presents the main steps to perform the logic synthesis of the VHDL RTL model with the SynopsysDesign Vision and Design Compiler tools. The sold alias displays the complete Synopsys documentationset. Manual pages are available by executing the command “snps man command” (e.g., snps man<strong>design</strong>_vision).3.1 Starting the Design Vision graphical environmentTo start the Synopsys Design Vision environment, enter the <strong>design</strong>_vision command in a new shell:[65]vachoux@lsmsun1-ADDSUB> <strong>design</strong>_visionhierarchywindow<strong>design</strong> informationconsole windowcommand lineThe command line is also echoed in the terminal shell from which the tool has been started, so it is possibleto enter DC commands from there as well (the shell has the <strong>design</strong>_vision-xg-t> prompt). It is still possibleto execute some Unix commands from here.AVx / version 3.1 - November 2006
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