Integrator/CP User Guide - ARM Information Center

Peripherals and Interfaces4.7.2 KMI functional overviewThis section provides a functional overview of the Keyboard and Mouse Interface(KMI). For detailed information about the KMI, see KMI (PL050) Technical ReferenceManual.The APB interface and register block provides the interface with the APB and controlregisters. All control register bits are synchronized to the main clock for KMI logicbefore they are used in the KMI core. This block also generates individual transmit andreceive interrupts.The transmit block converts the parallel transmit data into a serial bit stream with a ratedependent on the incoming KMI clock signal. This block performs odd paritygeneration, data framing, and parallel-to-serial conversion. This block operates onKMIREFCLK (that on the baseboard is supplied by CLK24MHz) with the incomingclock signal KMICLKIN providing the bit-rate information. The data is shifted out onthe falling edge of the KMICLKIN input.The receive block performs serial-to-parallel conversion on the serial data streamreceived on the KMIDATAIN input pin. The falling edge on the synchronized andsampled KMICLKIN input signal is used to sample the KMIDATAIN input line. TheKMIDATAIN input is synchronized to the KMIREFCLK clock.The controller controls transmit and receive operations. If simultaneous requests fortransmission and reception occur, the transmit request is given priority.4.7.3 KMI interruptsThe KMI generates the following interrupts:Transmit interruptThis is asserted to indicate that a byte can be written to the data registerKMIDATA for transmission.Receive interruptThis asserted to indicate that a byte has been received and can be readfrom the data register KMIDATA.A combined interrupt is also asserted if either the transmit or receive interrupt isasserted. This combined interrupt is used by the system interrupt controller.4-34 Copyright © 2002 ARM Limited. All rights reserved. ARM DUI 0159B