Integrator/CP User Guide - ARM Information Center

Peripherals and InterfacesLCD1_BIAS is a variable supply controlled by the MAX686 (U6, DAC-controlledboost/Inverter LCD bias supply) and switched ON and OFF by the MOSFET switch(U26). LCD1_BIAS is varied between 11.5V and 24V in 64 steps using the inputs onpins B9 and B17 on the HDRA socket. These are edge-triggered inputs. The MAX686is reset to the midpoint by a power-on reset. The MOSFET switch is controlled by theinput from B1. The bias control signals are enabled when B30 is LOW and disabledwhen B30 is HIGH.LCD0_3V3 and LCD1_3V3 are fixed-level power outputs that are controlled byMOSFET switches within U27. The switches are controlled by the signal on the pin B31of the HDRA connector.The power-control signal B31 is controlled by bit 11 in the LCD PrimeCell registerLCD_CTRL.The LCD bias controls are disabled when the VGA display interface is in 24-bit mode,when n24BITENis LOW. n24BITENmust be HIGH in order to adjust the LCD biascontrols.The signals from the HDRA connector in Figure 4-4 on page 4-7 are controlled by theCM_CTRL register in the system controller FPGA:B1 Bit 9 is LCDBIASUPB9 Bit 10 is LCDBIASDNB17 Bit 8 is LCDBIASENB30 Bit 19 is n24BITEN.4.3.3 Backlight powerConnector J5 can be used to supply power to an inverter for a cold-cathode LCDbacklight. The backlight supply pins VIN on J5 are supplied for the unregulated, fusedpower supply input to the CP. The backlight inverter must consume less than 5W.In addition to voltage and ground pins, the connector also supplies the brightnessadjustment voltage (0 to 2.5V) and shutdown logic signal (generated from the on/offswitch). The brightness is adjusted by a variable resistor, R26, located near J5.4.3.4 VGA display interfaceThe Integrator/CP provides a VGA display interface implemented with a THS8134Atriple DAC as shown in Figure 4-5 on page 4-9. The video DAC can be configured for24-bit (3x8 bit) or 16-bit RGB operation. The blanking and synchronization inputsignals are tied high to 3.3V. Pixel data and the horizontal and vertical synchronizationsignals are supplied by the display interface within the FPGA on the core module.4-8 Copyright © 2002 ARM Limited. All rights reserved. ARM DUI 0159B