Integrator/CP User Guide - ARM Information Center

Peripherals and InterfacesThe timing for VGA and SVGA outputs are shown in Table 4-3.Table 4-3 VGA and SVGA timingWaveformPart VGA (640x480) SVGA (800x600)One line Front porch 31 pixels 19 pixelsHorizontal sync. 63 pixels 164 pixelsBack porch 63 pixels 19 pixelsVideo 640 pixels 800 pixelsOne field Front porch 11 lines 5 linesVertical sync. 24 lines 61 linesBack porch 8 lines 5 linesVideo 480 lines 600 linesAux. Clock Frequency 25MHz. 36MHz4.3.5 Video frame bufferThe frame buffer is placed in SDRAM, for example at 0x00200000. The amount ofSDRAM used depends on the selected resolution and color depth.4.3.6 Color LCD registersThis section describes the color LCD registers, for more detail see the PrimeCell ColorLCD controller (PL110).The following locations are reserved, and must not be used during normal operation:• locations 0xC0000030 through 0xC00001FC are reserved for possible futureextensions• locations at offsets 0xC0000400 through 0xC00007FF are reserved for test purposes.4-10 Copyright © 2002 ARM Limited. All rights reserved. ARM DUI 0159B