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Integrator/CP User Guide - ARM Information Center

Integrator/CP User Guide - ARM Information Center

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Peripherals and Interfaces4.8.2 UART functional overviewThis section provides a functional overview of the UARTs. For detailed informationabout the UART, see the UART (PL011) Technical Reference Manual.Data for transmission is written into a 16-byte transmit FIFO and the UART startstransmitting data frames with the parameters defined in the UART line control register.Transmission continues until the FIFO is emptied.On the receive side, the UART begins sampling after it receives a start bit (LOW levelinput). When a complete word has been received, it is stored in the receive FIFOtogether with any error bits associated with that word. See Overview of UART registerson page 4-40 for details of the read FIFO bits.You can disable the FIFOs. In this case, the UART provides 1-byte holding registers forthe transmit and receive channels. The overrun bit in the UART_RSR register is set andan interrupt is generated if a byte is received before the previous one has been read.A feature of the UART means that the FIFOs are not physically disabled but arebypassed. This means that if an overrun error occurs, the excess data is still stored in theFIFO and must be read out to clear the FIFO.You set the baud rate of the UART by programming the bit rate divisor registersUART_LCRM and UART_LCRL.4.8.3 UART interruptsEach UART generates four interrupts. These are:Modem status interruptThis is asserted when any of the status lines (DCD, DSR, and CTS)change. It is cleared by writing to the UART_ICR register.UART disabled interruptThis is asserted when the UART is disabled and a start bit (low level) isdetected on the receive line. It is cleared if the UART is enabled or if thereceive line goes HIGH.Rx interruptThis is asserted when one of the following events occur:• the receive FIFO is enabled and the FIFO is half or more than halffull (contains eight or more bytes)• the receive FIFO is not empty and there has been no data for morethan a 32-bit period4-38 Copyright © 2002 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DUI 0159B

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