Integrator/CP User Guide - ARM Information Center

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Peripherals and InterfacesLCD1_BIAS is a variable supply controlled by the MAX686 (U6, DAC-controlledboost/Inverter LCD bias supply) and switched ON and OFF by the MOSFET switch(U26). LCD1_BIAS is varied between 11.5V and 24V in 64 steps using the inputs onpins B9 and B17 on the HDRA socket. These are edge-triggered inputs. The MAX686is reset to the midpoint by a power-on reset. The MOSFET switch is controlled by theinput from B1. The bias control signals are enabled when B30 is LOW and disabledwhen B30 is HIGH.LCD0_3V3 and LCD1_3V3 are fixed-level power outputs that are controlled byMOSFET switches within U27. The switches are controlled by the signal on the pin B31of the HDRA connector.The power-control signal B31 is controlled by bit 11 in the LCD PrimeCell registerLCD_CTRL.The LCD bias controls are disabled when the VGA display interface is in 24-bit mode,when n24BITENis LOW. n24BITENmust be HIGH in order to adjust the LCD biascontrols.The signals from the HDRA connector in Figure 4-4 on page 4-7 are controlled by theCM_CTRL register in the system controller FPGA:B1 Bit 9 is LCDBIASUPB9 Bit 10 is LCDBIASDNB17 Bit 8 is LCDBIASENB30 Bit 19 is n24BITEN.4.3.3 Backlight powerConnector J5 can be used to supply power to an inverter for a cold-cathode LCDbacklight. The backlight supply pins VIN on J5 are supplied for the unregulated, fusedpower supply input to the CP. The backlight inverter must consume less than 5W.In addition to voltage and ground pins, the connector also supplies the brightnessadjustment voltage (0 to 2.5V) and shutdown logic signal (generated from the on/offswitch). The brightness is adjusted by a variable resistor, R26, located near J5.4.3.4 VGA display interfaceThe Integrator/CP provides a VGA display interface implemented with a THS8134Atriple DAC as shown in Figure 4-5 on page 4-9. The video DAC can be configured for24-bit (3x8 bit) or 16-bit RGB operation. The blanking and synchronization inputsignals are tied high to 3.3V. Pixel data and the horizontal and vertical synchronizationsignals are supplied by the display interface within the FPGA on the core module.4-8 Copyright © 2002 ARM Limited. All rights reserved. ARM DUI 0159B
Peripherals and InterfacesThe 24-bit and 16-bit modes do not use the color palette. In 24-bit mode, colorinformation is organized 8-8-8 bits. In 16-bit mode, there is 1 bit for intensity, then 5-5-5bits for color.B[1:0]U4VGA_R[1:0]REDB[7:2] (Red)B[9:8]U4VGA_G[1:0]GREENHDRA SocketB[15:10] (Green)B[17:16]B[23:18] (Blue)B24 (VGA_CLK)U4VGA_B[1:0]VideoDAC(U22)BLUEHSYNCVSYNCJ15B25B26B30(n24BITENABLE)Figure 4-5 VGA interface architectureThe signal n24BITENABLE on B30 is used to enable the lower two bits on each of thethree color channels. These are enabled when n24BITENABLE is LOW and disabledwhen n24BITENABLE is HIGH.ARM DUI 0159B Copyright © 2002 ARM Limited. All rights reserved. 4-9
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®Integrator /CPCompact Platform Ba
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Conformance NoticesThis section con
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ContentsIntegrator/CP User GuidePre
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PrefaceThis preface introduces the
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PrefaceTypographical conventionsThe
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Preface• MultiMedia Card Product
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Chapter 1IntroductionThis chapter i
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IntroductionCore moduleBaseboardFig
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Introduction1.2.2 System connectors
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IntroductionCore module connectorsF
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IntroductionLED Color FunctionTable
Page 23 and 24: Introduction1.3.3 Care of connector
Page 25 and 26: Chapter 2Getting StartedThis sectio
Page 27 and 28: Getting Started2.1 Setting the DIP
Page 29 and 30: Getting StartedTable 2-2 shows the
Page 31 and 32: Getting Started2.4 System expansion
Page 34 and 35: Getting Started2.5.2 Possible effec
Page 36 and 37: Getting Started2.5.5 System informa
Page 38 and 39: System Architecture3.1 About the sy
Page 40 and 41: System ArchitectureNoteTable B-1 on
Page 42 and 43: System Architecture3.3 Module-assig
Page 44 and 45: System ArchitectureCFGSEL0CFGSEL1HI
Page 46 and 47: System ArchitectureThe APB is an AM
Page 48 and 49: System ArchitectureNoteThe copies o
Page 50 and 51: System Architecture3.6 Interrupt co
Page 52 and 53: System ArchitectureAn example of th
Page 54 and 55: System ArchitectureThe secondary co
Page 56 and 57: System ArchitectureNoteThe constant
Page 58 and 59: System ArchitecturenFIQ3 nFIQ0 nFIQ
Page 60 and 61: System Architecture3.8 Configuring
Page 62 and 63: System ArchitecturePeripheral Addre
Page 64 and 65: System ArchitectureCP_FLASHPROGThe
Page 66 and 67: System ArchitectureCP_DECODEBits 7
Page 68 and 69: Peripherals and Interfaces4.1 GPIO
Page 70 and 71: Peripherals and Interfaces4.2 Ether
Page 72 and 73: Peripherals and Interfaces4.3 Displ
Page 76 and 77: Peripherals and InterfacesThe timin
Page 78 and 79: Peripherals and InterfacesFor VGA o
Page 80 and 81: Peripherals and Interfaces4.4 Touch
Page 82 and 83: Peripherals and InterfacesTouchscre
Page 84 and 85: Peripherals and InterfacesTable 4-9
Page 86 and 87: Peripherals and Interfaces4.5 Audio
Page 88 and 89: Peripherals and InterfacesPRESETnPW
Page 90 and 91: Peripherals and InterfacesWhen the
Page 96 and 97: Peripherals and Interfaces4.6.2 Pri
Page 100 and 101: Peripherals and Interfaces4.7.2 KMI
Page 104 and 105: Peripherals and Interfaces4.8.2 UAR
Page 106 and 107: Peripherals and Interfaces4.8.5 Ove
Page 108 and 109: Peripherals and Interfaces4.9 Count
Page 114 and 115: Peripherals and Interfaces4.10 Debu
Page 118 and 119: Peripherals and Interfaces4-52 Copy
Page 120 and 121: System Expansion5.1 Expanding your
Page 122 and 123: System Expansion5-4 Copyright © 20
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Porting Integrator/AP and IM-PD1A.1
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Porting Integrator/AP and IM-PD1A.3
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Connector PinoutsB.1 Header connect
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Connector PinoutsB.1.2Baseboard con
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Connector PinoutsTable B-2 HDRB sig
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Connector Pinouts465321Figure B-4 K
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Connector PinoutsTable B-5 Generic
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Connector Pinouts1 2 3 4 56 7 8 9 1
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Connector PinoutsTable B-9 Touchscr
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Connector PinoutsB.2.6Ethernet debu
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Connector PinoutsLEDDATA_BUF12GNDnL
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Connector PinoutsMCI_112GNDMCI_2GND
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Connector PinoutsB-22 Copyright ©
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1 2 3 4OFFTest PointsC.1 Baseboard
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Test PointsC-4 Copyright © 2002 AR
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GlossaryDTEETMFIFOFPGAGPIOJTAGKMILC
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Indexregister bit assignments 3-16F
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IndexIndex-4 Copyright © 2002 ARM
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