Integrator/CP User Guide - ARM Information Center

System Architecture3.3 Module-assigned signalsA number of signals are routed between the HDRA and HDRB plug and socket on thecore module and logic modules so that they rotate up through the stack. The signalrotation allows interrupt and memory control based on the cards position in the stackwithout the requirement for changing jumpers on a board if its position in the stack ischanged.The signals that are rotated are:nIRQ[3:0]nFIQ[3:0]These are the interrupt request signals from the logic modules. They aredescribed in Interrupt controllers on page 3-14.These are the interrupt request signals from the logic modules. They aredescribed in Interrupt controllers on page 3-14.nPPRES[3:0]These are the module presence signals from the logic modules. Theyindicate to the address decoder that a logic module has been added to thesystem and is responsible for generating bus responses for its ownaddress space (see Register overview on page 3-25). On the logicmodules these signals correspond to the nEPRES[3:0] signals. On theIntegrator/CP, three logic modules can be added, but only one coremodule is permitted. See Logic module expansion memory space onpage 3-13.SYSCLK[3:0]These are the system bus clock signals rotated up through the stack toensure even distribution and signal loading.ID[3:0]The signals rotate up through the stack to indicate the position of a boardin the stack of modules. The signals are only used by optional logicmodules. Only one core module can be used and must always at thebottom of the stack.3-6 Copyright © 2002 ARM Limited. All rights reserved. ARM DUI 0159B