Integrator/CP User Guide - ARM Information Center

Connector PinoutsTable B-2 HDRB signal descriptionPin labelSignal NameCPspecificDescriptionE[31:28] HCLK[3:0] - System clock to the core module.E[27:24] nPPRES[3:0] Yes Core Module present.Each core module ties nPPRES[0] LOW andleaves nPPRES[3:1] open circuit. These signalsrotate as they move up or down the stack so thatthere is a connection between each module andone of these signals at the system controller on thebaseboard. Only one core module however, ispermitted in the Integrator/CP system.E[23:20] nIRQ[3:0] - Interrupt request to processor.E[19:16] nFIQ[3:0] - Fast interrupt requests to processor.E[15:12] ID[3:0] Yes Core Module stack position indicator. Only onecore module however, is permitted in theIntegrator/CP system.E[11:8] HLOCK[3:0] Yes System bus lock from processor, but only a singlecore module is permitted.E[7:4] HGRANT[3:0] Yes System bus grant to processor, but only a singlecore module is permitted.E[3:0] HBUSREQ[3:0] Yes System bus request from processor, but only asingle core module is permitted.F[31:16] andF[9:8]- Yes A variety of interface connectionsF[15:10] - Yes MMC interface signalsF[13] and F[7:5] - Yes Audio codec signalF[4:0] - Yes Touchscreen host interface signalsG16 nRTCKEN - RTCK AND gate enable.G[15:14] CFGSEL[1:0] - FPGA configuration select.G13 nCFGEN - Sets system into configuration mode.G12 nSRST - Multi-ICE reset (open collector).G11 FPGADONE - Indicates when FPGA configuration is complete.ARM DUI 0159B Copyright © 2002 ARM Limited. All rights reserved. B-5