Integrator/CP User Guide - ARM Information Center
Integrator/CP User Guide - ARM Information Center
Integrator/CP User Guide - ARM Information Center
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Peripherals and InterfacesTimer x interrupt status registerBit 0 of this register indicates the masked interrupt status from the counter. This valueis the logical AND of the raw interrupt status with the timer interrupt enable bit fromthe control register, and is the same value that is passed to the interrupt output pin.Table 4-21 shows the bit assignments for the TimerXMIS register.Bit Name Type FunctionTable 4-21 TimerXMIS register[0] Timer Interrupt Read Enabled interrupt status from the counter<strong>ARM</strong> DUI 0159B Copyright © 2002 <strong>ARM</strong> Limited. All rights reserved. 4-47
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