M16C User Manual.pdf

Serial I/OMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERUART transmit/receive control register 2b7 b6 b5 b4 b3 b2 b1 b0Symbol Address When resetUCON 03B016 X00000002BitsymbolU0IRSU1IRSU0RRMU1RRMCLKMD0CLKMD1RCSPUART2 special mode registerBitnameUART0 transmitinterrupt cause select bitUART1 transmitinterrupt cause select bitUART0 continuousreceive mode enable bitUART1 continuousreceive mode enable bitCLK/CLKS select bit 0CLK/CLKS selectbit 1 (Note)Separate CTS/RTS bitFunction(During clock synchronousserial I/O mode)0 : Transmit buffer empty (Tl = 1)1 : Transmission completed(TXEPT = 1)0 : Transmit buffer empty (Tl = 1)1 : Transmission completed(TXEPT = 1)0 : Continuous receivemode disabled1 : Continuous receivemode enable0 : Continuous receivemode disabled1 : Continuous receivemode enabledValid when bit 5 = “1”0 : Clock output to CLK11 : Clock output to CLKS10 : Normal mode(CLK output is CLK1 only)1 : Transfer clock outputfrom multiple pinsfunction selected0 : CTS/RTS shared pin1 : CTS/RTS separatedFunction(During UART mode)0 : Transmit buffer empty (Tl = 1)1 : Transmission completed(TXEPT = 1)0 : Transmit buffer empty (Tl = 1)1 : Transmission completed(TXEPT = 1)InvalidInvalidInvalidMust always be “0”0 : CTS/RTS shared pin1 : CTS/RTS separatedNothing is assigned.In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.Note: When using multiple pins to output the transfer clock, the following requirements must be met:• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”.R W b7 b6 b5 b4 b3 b2 b1 b00Symbol Address When resetU2SMR 037716 0016BitsymbolIICMABCBBSLSYNABSCSACSESSSBitnameIIC mode selection bitArbitration lost detectingflag control bitBus busy flagSCLL sync outputenable bitBus collision detectsamplingclock select bitAuto clear functionselect bit of transmitenable bitTransmit start conditionselect bitFunction(During clock synchronousserial I/O mode)0 : Normal mode1 : IIC mode0 : Update per bit1 : Update per byte0 : STOP condition detected1 : START condition detected0 : Disabled1 : EnabledMust always be “0”Must always be “0”Must always be “0”Function(During UART mode)Must always be “0”Must always be “0”Must always be “0”Must always be “0”0 : Rising edge of transferclock1 : Underflow signal of timer A00 : No auto clear function1 : Auto clear at occurrence ofbus collision0 : Ordinary1 : Falling edge of RxD2R W(Note) Reserved bit Always set to “0”Note: Nothing but "0" may be written.Figure 1.19.8. Serial I/O-related registers (5)121