M16C User Manual.pdf

Clock-Synchronous Serial I/OMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER2.4.4 Operation of Serial I/O (reception in clock-synchronous serial I/O mode)In receiving data in clock-synchronous serial I/O mode, choose functions from those listed in Table 2.4.3.Operations of the circled items are described below. Figure 2.4.13 shows the operation timing, and Figures2.4.14 and 2.4.15 show the set-up procedures.Table 2.4.3. Choosed functionsItemSet-upItemSet-upTransfer clocksourceOInternal clock (f1 / f8 / f32)External clock (CLKi pin)Continuous receivemodeODisabledEnabledRTS functionORTS function enabledRTS function disabledOutput transfer clockto multiple pins(Note 1)ONot selectedSelectedCLK polarityOInput reception data atthe rising edge of thetransfer clockCTS / RTSseparation function(Note 2)OPin shared by CTS and RTSCTS and RTS separatedInput reception data atthe falling edge of thetransfer clockData logic selectfunction(Note 3)ONo reverseReverseTransfer clockOLSB firstMSB firstTXD, RXD I/Opolarity reverse bit(Note 3)ONo reverseReverseNote 1: This can be selected only when UART1 is used in combination with the internal clock. When this function is_______ ______________ _______selected, neither UART1 CTS/RTS function, nor UART0 CTS/RTS separation function can be utilized. Set the_______ _______UART1 CTS/RTS disable bit to “1”._______ _______Note 2: UART0 only. (UART1 CTS/RTS function cannot be used when this function is selected.)Note 3: UART2 only.Operation (1) Writing dummy data to the UARTi transmit buffer register, setting the receive enable bit to “1”,and the transmit enable bit to “1”, makes the data receivable status ready. At this time, the________output from the RTSi pin goes to “L” level, which informs the transmission side that the datareceivable status is ready (output the transfer clock from the IC on the transmission side after_______checking that the RTS output has gone to “L” level).(2) In synchronization with the first rising edge of the transfer clock, the input signal to the RxDipin is stored in the highest bit of the UARTi receive register. Then, data is taken in by shiftingright the content of the UARTi reception data in synchronization with the rising edges of thetransfer clock.(3) When 1-byte data lines up in the UARTi receive register, the content of the UARTi receiveregister is transmitted to the UARTi receive buffer register. The transfer clock stops at “H”level. At this time, the receive complete flag and the UARTi receive interrupt request bit goesto “1”.(4) The receive complete flag goes to “0” when the lower-order byte of the UARTi buffer registeris read.342