M16C User Manual.pdf

InterruptMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER4.2.1 Interrupt Enable FlagThe interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting thisflag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is setto “0” after reset.The content is changed when the I flag is changed causes the acceptance of the interrupt request in thefollowing timing:• When changing the I flag using the REIT instruction, the acceptance of the interrupt takeseffect as the REIT instruction is executed.• When changing the I flag using one of the FCLR, FSET, POPC, and LDC instructions, theacceptance of the interrupt is effective as the next instruction is executed.When changed by REIT instructionInterrupt request generatedDetermination whether or not toaccept interrupt requestTimePreviousinstructionREITInterrupt sequence(If I flag is changed from 0 to 1 by REIT instruction)When changed by FCLR, FSET, POPC, or LDC instructionInterrupt request generatedDetermination whether or not toaccept interrupt requestTimePreviousinstructionFSET INext instructionInterrupt sequence(If I flag is changed from 0 to 1 by FSET instruction)Figure 4.2.3. The timing of reflecting the change in the I flag to the interrupt4.2.2 Interrupt Request BitThe interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt isaccepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. Theinterrupt request bit can also be set to "0" by software. (Do not set this bit to "1").493