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M16C User Manual.pdf

M16C User Manual.pdf

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Clock-Synchronous Serial I/OMitsubishi microcomputers<strong>M16C</strong> / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERUARTi transmit/receive mode registerb7 b6 b5 b4 b3 b2 b1 b0Symbol Address When resetUiMR(i=0,1) 03A016, 03A816 0016BitsymbolSMD0SMD1SMD2CKDIRSTPSPRYPRYESLEPBit nameSerial I/O mode select bitInternal/external clockselect bitStop bit length select bitOdd/even parity select bitParity enable bitSleep select bitFunction(During clock synchronousserial I/O mode)Must be fixed to 001b2 b1 b00 0 0 : Serial I/O invalid0 1 0 : Inhibited0 1 1 : Inhibited1 1 1 : Inhibited0 : Internal clock1 : External clock (Note)InvalidInvalidInvalidMust always be “0”Note : Set the corresponding port direction register to “0”.b2 b1 b0Function(During UART mode)1 0 0 : Transfer data 7 bits long1 0 1 : Transfer data 8 bits long1 1 0 : Transfer data 9 bits long0 0 0 : Serial I/O invalid0 1 0 : Inhibited0 1 1 : Inhibited1 1 1 : Inhibited0 : Internal clock1 : External clock (Note)0 : One stop bit1 : Two stop bitsValid when bit 6 = “1”0 : Odd parity1 : Even parity0 : Parity disabled1 : Parity enabled0 : Sleep mode deselected1 : Sleep mode selectedR W UART2 transmit/receive mode registerb7 b6 b5 b4 b3 b2 b1 b0Symbol Address When resetU2MR 037816 0016BitsymbolSMD0SMD1SMD2CKDIRSTPSPRYPRYEIOPOLBit nameSerial I/O mode select bitInternal/external clockselect bitStop bit length select bitOdd/even parity select bitParity enable bitTxD, RxD I/O polarityreverse bitFunction(During clock synchronousserial I/O mode)Must be fixed to 001b2 b1 b00 0 0 : Serial I/O invalid0 1 0 : (Note 1)0 1 1 : Inhibited1 1 1 : Inhibited0 : Internal clock1 : External clock (Note 2)InvalidInvalidInvalid0 : No reverse1 : ReverseUsually set to “0”Note 1: Bit 2 to bit 0 are set to “0102” when I 2 C mode is used.Note 2: Set the corresponding port direction register to “0”.b2 b1 b0Function(During UART mode)1 0 0 : Transfer data 7 bits long1 0 1 : Transfer data 8 bits long1 1 0 : Transfer data 9 bits long0 0 0 : Serial I/O invalid0 1 0 : Inhibited0 1 1 : Inhibited1 1 1 : InhibitedMust always be fixed to “0”0 : One stop bit1 : Two stop bitsValid when bit 6 = “1”0 : Odd parity1 : Even parity0 : Parity disabled1 : Parity enabled0 : No reverse1 : ReverseUsually set to “0”R W Figure 2.4.3. Serial I/O-related registers (2)330

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