M16C User Manual.pdf

Power ControlMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER(5) Sequence of returning from stop modeSequence of returning from stop mode is oscillation start-up time and interrupt sequence.When interrupt is generated in stop mode, CM10 becomes “0” and clearing stop mode.Starting oscillation and supplying BCLK execute the interrupt sequence as follow:In the interrupt sequence, the processor carries out the following in sequence given:(a) CPU gets the interrupt information (the interrupt number and interrupt request level) by readingaddress 0000016. The interrupt request bit of the interrupt written in address 0000016 willthen be set to “0”.(b) Saves the content of the flag register (FLG) as it was immediately before the start of interruptsequence in the temporary register (Note) within the CPU.(c) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer assignmentflag (U flag) to “0” (the U flag, however does not change if the INT instruction, in softwareinterrupt numbers 32 through 63, is executed)(d) Saves the content of the temporary register (Note) within the CPU in the stack area.(e) Saves the content of the program counter (PC) in the stack area.(f) Sets the interrupt priority level of the accepted instruction in the IPL.Note: This register cannot be utilized by the user.After the interrupt sequence is completed, the processor resumes executing instructionsfrom the first address of the interrupt routine.Figure 2.14.2 shows the sequence of returning from stop mode.Writing “1” to CM10(all clock stop control bit)Operated by divided-by-8 modeBCLKAddress busAddress00000Indeterminate SP-2 SP-4 vec vec+2PCData busInterruptinformationIndeterminateSP-2contentsSP-4contentsveccontentsvec+2contentsRDIndeterminateWRINTiStop modeOscillation start-upInterrupt sequence approximately 20 cycle (13µ sec)(Single-chip mode, f(XIN) = 16MHz)Note: Shown above is the case where the main clock is selected for BCLK. If the sub-clock is selected for BCLK,the sub-clock functions as BCLK when restored from stop mode, with the main clock's divide ratiounchanged.Figure 2.14.2. Sequence of returning from stop mode(6) Registers related to power controlFigure 2.14.3 shows the memory map of power control-related registers, and Figure 2.14.4 showspower control-related registers.000616000716System clock control register 0 (CM0)System clock control register 1 (CM1)Figure 2.14.3. Memory map of power control-related registers441