M16C User Manual.pdf

DMACMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER2.9.3 Operation of DMAC (repeated transfer mode)In repeat transfer mode, choose functions from the items shown in Table 2.9.2. Operations of the circleditems are described below. Figure 2.9.6 shows an example of operation and Figure 2.9.7 shows the setupprocedure.Table 2.9.2. Choosed functionsItemSet-upTransfer spaceUnit of transferOOFixed address from an arbitrary 1 M bytes spaceArbitrary 1 M bytes space from a fixed addressFixed address from fixed address8 bits16 bitsOperation(1) When software trigger is selected, setting software DMA request bit to “1” generates a DMAtransfer request signal.(2) If DMAC is active, data transfer starts, and the contents of the address indicated by the DMAiforward-direction address pointer are transferred to the address indicated by the DMAi destinationpointer. When data transfer starts directly after DMAC becomes active, the value ofthe DMAi transfer counter reload register is reloaded to the DMAi transfer counter, and thevalue of the DMAi source pointer is reloaded by the DMAi forward-direction address pointer.Each time a DMA transfer request signal is generated, 2 byte of data is transferred. TheDMAi transfer counter is down counted, and the DMAi forward-direction address pointer is upcounted.(3) Though DMAi transfer counter is underflowed, DMA enable bit is still “1”. The DMA interruptrequest bit changes to “1” simultaneously.(4) After DMAi transfer counter is underflowed, when the next DMA request is generated, DMAtransfer is repeated from (1).(1) Request signal for a DMA transfer occurs(2) Data transfer begins(3) UnderflowBCLKDestinationDummy cycleDestination Dummy cycleDestination Dummy cycleAddress busCPU useSourceCPU useSourceCPU useSourceCPU useRD signalWR signalDestinationDummy cycleDestinationDummy cycleDestinationDummy cycleData busCPU useSourceCPU useSourceCPU useSourceCPU useWrite signal tosoftware DMAirequest bitDMAirequest bit0116 0116DMA transfercounterIndeterminate 0016FF160016DMAiinterruptrequest bitCleared to “0” when interrupt request is accepted, or cleared by softwareDMAi“1”enable bit • In the case in which the number of transfer times is set to 2.Figure 2.9.6. Example of operation of repeated transfer mode422