M16C User Manual.pdf

InterruptMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER4.6 Multiple InterruptsThe state when control branched to an interrupt routine is described below:· The interrupt enable flag (I flag) is set to “0” (the interrupt is disabled).· The interrupt request bit of the accepted interrupt is set to “0”.· The processor interrupt priority level (IPL) is assigned to the same interrupt priority level as assigned tothe accepted interrupt.Setting the interrupt enable flag (I flag) to “1” within an interrupt routine allows an interrupt request assigneda priority higher than the IPL to be accepted. Figure 4.6.1 shows the scheme of multiple interrupts.An interrupt request that is not accepted because of low priority will be held. If the condition following is metwhen the REIT instruction returns the IPL and the interrupt priority is determined, then the interrupt requestbeing held is accepted.Interrupt priority level of the interrupt request being held > Returned the IPL502