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M16C User Manual.pdf

M16C User Manual.pdf

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DMACMitsubishi microcomputers<strong>M16C</strong> / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER2.9.2 Operation of DMAC (one-shot transfer mode)In one-shot transfer mode, choose functions from the items shown in Table 2.9.1. Operations of thecircled items are described below. Figure 2.9.4 shows an example of operation and Figure 2.9.5shows the set-up procedure.Table 2.9.1. Choosed functionsItemSet-upTransfer spaceUnit of transferOOFixed address from an arbitrary 1 M bytes spaceArbitrary 1 M bytes space from a fixed addressFixed address from fixed address8 bits16 bitsOperation (1) When software trigger is selected, setting software DMA request bit to “1” generates a DMAtransfer request signal.(2) If DMAC is active, data transfer starts, and the contents of the address indicated by the DMAiforward-direction address pointer are transferred to the address indicated by the DMAi destinationpointer. When data transfer starts directly after DMAC becomes active, the value ofthe DMAi transfer counter reload register is reloaded to the DMAi transfer counter, and thevalue of the DMAi source pointer is reloaded by the DMAi forward-direction address pointer.Each time a DMA transfer request signal is generated, 1 byte of data is transferred. TheDMAi transfer counter is down counted, and the DMAi forward-direction address pointer is upcounted.(3) If the DMA transfer counter underflows, the DMA enable bit changes to “0” and DMA transferis completed. The DMA interrupt request bit changes to “1” simultaneously.(1) Request signal for a DMA transfer occurs(2) Data transfer begins(3) UnderflowBCLKDestinationDestinationAddress busCPU useSourceDummycycleCPU useSourceDummycycleCPU useRD signalWR signalDestinationDestinationData busCPU useSourceDummycycleCPU useSourceDummycycleCPU useWrite signal tosoftware DMAirequest bitDMAirequest bitDMA transfercounterIndeterminate 0016FF16DMAiinterruptrequest bitDMAienable bit0116• In the case in which the number of transfer times is set to 2.Cleared to “0” when interrupt request isaccepted, or cleared by softwareFigure 2.9.4. Example of operation of one-shot transfer mode420

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